Sigasi, an EDA company focused on agile hardware design tools, announced that it will make Sigasi HDT, an Intelligent Development Environment (IDE) for VHDL, available as an Eclipse plugin. As of today, Sigasi HDT will be available in two versions: as a standalone application as before, and as an Eclipse plugin. A tool license includes the right to use either version, at any time, at the customer’s discretion.
Oasys Design Systems announced that RealTime Designer[tm], Chip Synthesis[tm] software capable of synthesizing register transfer level (RTL) code for 100-million gate designs, now includes support for VHDL through de facto standard front-end software from Verific Design Automation. Verific licensed its VHDL analyzer to Oasys, giving RealTime Designer a common, proven and reliable front end for its unique Physical RTL synthesis. RealTime Designer is in production flows at leading-edge semiconductor and systems companies worldwide.
Aldec Corporation, a leader in RTL Simulation and Electronic Design Automation (EDA), announced a low-cost Linux RTL Simulator. Aldec unveils a new configuration that supports both Linux and Windows® mixed-language VHDL/Verilog® simulation. Riviera-PRO[TM] LV is a multi-platform RTL and gate-level simulator that supports IEEE VHDL, Verilog® and SystemVerilog (Design) IEEE standard, Xilinx SecureIP, and VHDL/Verilog IP encryption.