Tag Archives: TSMC

Cadence, ARM Team on Cortex-A57 64-bit Processor for TSMC 16nm FinFET Process

ARM and Cadence Design Systems teamed on the first ARM Cortex-A57 processor for TSMC’s 16-nanometer (nm) FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros. Their joint innovations will enable engineers to accelerate product development cycles and take advantage of leading-edge processes and IP.

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Cadence DFM Services for TSMC 40-nanometer Technology and Below

Cadence Design Systems introduced DFM Services for TSMC 40-nanometer technology and below. The design-for-manufacturing (DFM) services include model-based simulation of litho-process checks (LPC) and virtual chemical mechanical polishing (CMP) verification for designs down to 28nm. The goal is to help design teams effectively detect litho or CMP hotspots and fix them prior to tapeout. Cadence DFM Services feature turnkey access to DFM analysis based on TSMC’s DFM Data Kit (DDK), and DFM Services output analysis reports.

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Synopsys IC Validator Qualifies for TSMC 40nm, 65nm iDRC/iLVS Runsets

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that its IC Validator physical verification product is qualified for TSMC’s 40nm and 65nm interoperable DRC/LVS runsets, and is immediately available to TSMC customers. IC Validator, part of the Galaxy[tm] Implementation Platform, is an ideal add-on to IC Compiler for In-Design physical verification. By enabling physical verification within the implementation flow, IC Validator enables place and route engineers to accelerate time to tapeout and improve manufacturability. TSMC’s qualification of IC Validator brings the unique advantages of the In-Design flow to the broad range of design teams utilizing TSMC’s 40-nm and 65-nm process technologies.

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Atrenta, TSMC Team on Synthesizable IP for SpyGlass Platform

Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, disclosed details of a collaboration with TSMC to enhance the quality of delivered synthesizable IP using Atrenta’s SpyGlass® platform. SpyGlass is Atrenta’s register transfer level (RTL) analysis and optimization product suite that analyzes and optimizes the quality of integrated circuit designs early in the design process, before expensive and time-consuming physical implementation begins.

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MIPS, Open-Silicon, Dolphin Tapeout ASIC CPU at 2.4GHz and Beyond

Open-Silicon, Inc., MIPS Technologies, Inc. (NASDAQ: MIPS), and Dolphin Technology announced the successful tapeout of a high-performance ASIC processor at over 2.4GHz under typical conditions. This achievement, as measured in timing closure against TSMC reference flow signoff conditions, will make this one of the highest frequency ASIC processors ever built, highlighting the companies’ industry-leading technologies for building high-performance processor-based systems. This high-performance ASIC processor is a follow-on test chip to the 65nm, 1.1GHz test chip announced by Open-Silicon and MIPS Technologies at the end of last year.

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TSMC Reference Flow 11 Features XtractIM, OrbitIO Planner, OptimizePI

Sigrity, Inc., the market leader in signal and power integrity solutions, announced that TSMC has included three Sigrity chip, package and system co-design products – XtractIM, OrbitIO Planner and OptimizePI – in its new TSMC Reference Flow 11.0. Companies that rely on TSMC flow support now can benefit from streamlined IC package assessment, package model extraction, chip/system IO planning, and power delivery system optimization.

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TSMC Reference Flow 11.0 Supports Arteris Network-on-Chip Interconnect IP

Arteris, Inc., the leading interconnect IP solutions provider, announced that its Network-on-Chip (NoC) interconnect IP and tools will be available to TSMC customers as part of TSMC Reference Flow 11.0, the foundry’s latest design reference flow for its advanced process technology. The TSMC support for Arteris Network-on-Chip (NoC) interconnect IP is a milestone where a silicon foundry has incorporated an interconnect IP solution into a reference flow, providing designers with an efficient way to manage the complexity and performance of highly integrated SoC’s. Arteris ships a commercial NoC IP solution and its NoC-connected SoCs are incorporated in commercially available systems, such as LCD projectors and Digital Televisions.

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TSMC Reference Flow 11 Features Carbon Model Studio, SoC Designer Plus

Carbon Design Systems announced that TSMC added Carbon Model Studio and SoC Designer Plus to TSMC Reference Flow 11.0. The Carbon products used in Reference Flow 11.0 support performance and power analysis at the System (ESL) and register transfer level (RTL), and also provide a platform for pre-silicon software development.

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TSMC Validates Magma Titan and FineSim for AMS Reference Flow

Magma® Design Automation (Nasdaq: LAVA), a provider of chip design software, announced TSMC has validated the Titan[tm] Mixed-Signal Design Platform and FineSim[tm] SPICE and FineSim Pro circuit simulation products for TSMC’s first Analog/Mixed-Signal (AMS) Reference Flow inclusion, targeting its most advanced 28-nanometer (nm) process technology. The TSMC AMS Reference Flow 1.0 aims to address advanced process effects to accelerate next-generation analog/mixed-signal IC designs. The combination of the AMS Reference Flow and Magma’s Titan Mixed-Signal Design Platform and FineSim circuit simulator provide users with an integrated front-end and back-end analog design solution that accelerates time-to-market by improving designer productivity and enabling analog design reuse.

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TSMC Reduces Logic Area By 15% with Standard Cell Slim Library

Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) introduced the first Slim Library that reduces system-on-chip (SoC) routed logic block area by 15 percent compared to blocks routed through current standard cell libraries. The library targets TSMC’s 65nm LP process technology and fits existing implementation flows for easy adoption. Designers can use the new Slim Library in existing or new designs without change to design tools and implementation methodologies.

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