Tag Archives: Testing

New eBook: Testing DDR3 Memory Boundary Scan JTAG

Testing DDR3 Memory Boundary Scan JTAG eBook | ASSET InterTech

ASSET InterTech published a new eBook. The publication explains how to test DDR memory with non-intrusive JTAG or boundary-scan (IEEE 1149.1) methods. The title of the paper is Testing DDR3 Memory Boundary Scan JTAG. The paper was written by Kent Zetterberg, product manager, ASSET InterTech.

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White Paper: How to test high-speed memory with non-intrusive embedded instruments

How to test high-speed memory with non-intrusive embedded instruments white paper

ASSET InterTech published a new white paper about non-intrusive embedded instruments. The technical paper explains how non-intrusive software-driven embedded instruments can overcome many of the challenges of testing, validating and debugging high-speed memory buses such the DDR 3 or DDR4 (DDR3/4) buses, and others. The title of their article is “How to test high-speed memory with non-intrusive embedded instruments.”

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Imec and Cadence Automated Test Solution for 3D Stacked ICs

Cadence Design Systems and imec teamed together to develop technology for testing 3D stacked ICs (3D-ICs). Their automated test solution makes it easier to test 3D-ICs with through-silicon via (TSV) functionality and helps ensure that the stacked system will work as intended. The solution includes design-for-test (DFT) and automatic test pattern generation (ATPG) technology.

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Mentor Graphics Reveals 3D-IC Strategy

Mentor Graphics revealed its 3D-IC strategy for designing, verifying, manufacturing and testing integrated circuit products using multi-die vertical stacking technology. Mentor also announced their 3D-IC testing solution, which includes multiple components of the Tessent design-for-test product line for integrated multi-die hierarchical scan and built-in self-test (BIST) methodologies. 3D-IC is an alternative to traditional scaling for achieving advances in performance, reduced power consumption, cost reduction, and increased functionality in a small package.

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Synopsys DesignWare SATA IP Passes SATA-IO Interoperability Testing

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Synopsys’ DesignWare® Serial Advanced Technology Attachment (SATA) IP solution has successfully passed the SATA International Organization (SATA-IO) electrical, digital and system interoperability testing for 130- to 40-nanometer (nm) process technologies. The SATA-IO interoperability testing validates Synopsys’ internal testing of the DesignWare SATA IP, which includes extensive digital and mixed-signal simulation validation, hardware FPGA-based prototyping using Synopsys’ HAPS® solution, and PHY test chip silicon characterization.

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