Cadence Design Systems acquired Tensilica for about $380 million in cash. Tensilica is a leader in dataplane processor IP core licensing with over 200 licensees. Tensilica’s configurable dataplane processing units are optimized for embedded data and signal processing. The IP cores are ideal for mobile wireless, network infrastructure, auto infotainment and home applications. As of December 31, 2012, Tensilica had approximately $30 million in cash.
Tensilica,® Inc. announced that it is the first IP (intellectual property) company with an audio core for system-on-chip (SOC) designs approved for using the Dolby® MS10 Multistream Decoder, a multi-format audio decoding technology that supports Dolby Digital Plus and Dolby Pulse in a single package for next-generation HDTVs (high-definition televisions), STBs (set-top boxes) and DMPs (digital media players).
Tensilica,® Inc. and Express Logic, Inc. announced that Express Logic’s ThreadX® real-time operating system (RTOS) is now available for Tensilica’s new third-generation Diamond Standard dataplane processor (DPU) cores. A free demo download of the ThreadX RTOS is available on the Tensilica web site. Designed for small-footprint, demanding real-time control, the ThreadX RTOS is a perfect match for the Diamond Standard family of general-purpose, low-power cores aimed at deeply embedded control and signal processing functions.
MIPS Technologies, Inc. (Nasdaq: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, announced it is working with leading providers of key IP for the connected digital home-including audio, video, graphics and security functionality-to help SoC developers get to market quickly with fully-integrated hardware/software solutions. MIPS is working closely with Chips & Media, Discretix, Tensilica, Vivante Corp. and other leading providers of semiconductor IP to help customers meet cost/performance targets with solutions that optimize performance for devices based in particular on the Android platform.
MIPS Technologies, Inc. (Nasdaq: MIPS) and Tensilica® Inc. announced they are working together to accelerate SOC (system-on-chip) design activity on the popular Android platform. Together, MIPS and Tensilica will help companies speed the design of new home entertainment and mobile consumer products based on Android. A joint demo of a MIPS32® processor core integrated with Tensilica’s HiFi 2 Audio DSP will be on display in suites that both companies have at the Consumer Electronics Show in Las Vegas, January 7-10, 2010.
Tensilica® Inc. announced its eighth generation tools that further automate customized Xtensa® dataplane processor (DPU) design and speed software development. Improvements cover improved compiler technology, better multi-core system simulation and profiling, an upgraded integrated development environment (IDE), and pin-level co-simulation with RTL. These enhancements further strengthen Tensilica’s leading position as the highest performance, and most complete, customizable processor core solution for SOC (system-on-chip) designs.
Tensilica,® Inc. announced that it now provides out-of-the-box automated design flow support for key technologies within Synopsys’ Galaxy[tm] Implementation Platform, including DC Ultra RTL synthesis and IC Compiler place-and-route, for Tensilica’s new Xtensa 8 and Xtensa LX3 dataplane processors (DPUs). This latest design flow provides up to 15 percent improvement in processor speed, area and power, in addition to faster design closure over previous Synopsys-based design flows, thus offering immediate benefits to Tensilica customers.