Tag Archives: SEMATECH

Researchers Enable III-V Technology for High Volume Manufacturing

Researchers have made significant advances in post-epitaxial growth backside clean processing. The research will prepare III-V technology for high-volume manufacturing. The research leading to these accomplishments was conducted at SEMATECH’s facilities at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York.

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SEMATECH Makes Breakthrough in Reducing Defects in Extreme Ultraviolet Lithography

SEMATECH researchers have made a breakthrough in reducing tool-generated defects from multi-layer deposition of mask blanks used for extreme ultraviolet lithography (EUVL). The breakthrough brings EUVL technology a step closer to high-volume manufacturing. SEMATECH is an international consortium of leading semiconductor device, equipment, and materials manufacturers.

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International SEMATECH Manufacturing Initiative Publishes Fab Energy Study

The International SEMATECH Manufacturing Initiative recently published the results of their Worldwide Fab Energy Study. The research includes benchmark data to help identify the areas to reduce energy use and improve efficiency in semiconductor manufacturing operations. According to the study, there was a big a decrease in normalized fab energy consumption from 1997 to 2011. The ISMI Worldwide Fab Energy Study was conducted at 300 mm and 200 mm semiconductor manufacturing facilities in Asia, North America, and Europe.

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SEMATECH Presents Research Papers at VLSI-TSA Symposium

SEMATECH recently presented nine research papers at the International VLSI Technology, System and Applications Symposium (VLSI-TSA). The SEMATECH researchers reported on innovative materials and new transistor structures to address key aspects of transistor performance, power, and cost. The white papers outlined leading-edge research in high-k/metal gate (HKMG) materials, resistive RAM (RRAM) memory, and planar and non-planar CMOS technologies.

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SEMATECH 3D EC, SIA, SRC Team on 3D integration Technology

SEMATECH’s 3D Enablement Center (3D EC), the Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC) have identified the top technical challenges for new killer applications to enable future development of heterogeneous 3D integration beyond mobile wide I/O DRAM. Addressing the common challenges of next generation applications is critical for acceleration of the broad adoption of 3D ICs. The goal of the three organizations is to fully realize 3D integration for semiconductor manufacturing and design.

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SEMATECH Develops Bond Process for 3D IC Applications

SEMATECH developed a die-to-wafer interconnect process using a die-tacking and collective-bonding approach on a 300mm wafer platform for 3D-IC applications. Composite wafers containing a 50µm thin through-silicon-via (TSV) wafer attached to a supporting handle wafer were populated with dice using a short, low-temperature tacking process. SEMATECH presented their wafer bonding research at the Device Packaging Conference (DPC).

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SEMATECH, SIA and SRC Form 3D Enablement Program

SEMATECH, the Semiconductor Industry Association (SIA), and Semiconductor Research Corporation (SRC) announced they have established a new 3D Enablement program to drive cohesive industry standardization efforts and technical specifications for heterogeneous 3D integration. Administered by SEMATECH’s 3D Interconnect program, based at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, working in partnership with SRC, the program aims to establish the infrastructure necessary for the industry to leverage 3D packaging technology for innovative new applications.

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SEMATECH to Report on Resistive RAM Memory and FinFET Devices at IEDM

Revealing research breakthroughs, engineers from SEMATECH’s Front End Processes (FEP) program will present technical papers at the 56th annual IEEE International Electron Devices Meeting (IEDM) from December 6-8, 2010, at the Hilton in San Francisco, CA. SEMATECH experts will report on resistive RAM (RRAM) memory technologies, advanced Fin and nanowire FETs for scaled CMOS devices, high mobility III-V channel materials on 200mm silicon wafers in an industry standard MOSFET flow, and future ultra-low power tunneling FET devices — highlighting significant breakthroughs that address the growing need for higher performance and low power devices.

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SEMATECH Gate-Stack Symposium: To Sub-16nm Node and Beyond

Participants at the recent 7th Annual International Symposium on Advanced Gate Stack Technology discussed strategies for implementing advanced logic and memory technologies for sub-16 nm node and beyond process technologies. The Symposium, hosted by SEMATECH, drew more than 100 international researchers from industry and academia that shared recent discoveries and outlined new gate stack strategies for the 16nm technology generation and beyond.

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ISMI Symposium on Manufacturing Effectiveness Features Business Case for ESH

International SEMATECH Manufacturing Initiative (ISMI) will host a panel discussion entitled “The Business Case for ESH” at its 7th Annual ISMI Symposium on Manufacturing Effectiveness, scheduled to take place at the Renaissance Austin Hotel in Austin, October 31 – November 4, 2010. The panel discussion, to be held on Thursday, November 4, at 1:45 p.m., will be moderated by founder and director of weSRCH.com, G. Dan Hutcheson, and will feature a diverse group of senior executives who will share the benefits of sustainable business practices and functional models that apply to real-world semiconductor manufacturing environments.

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