Tag Archives: Design Flow

White Paper: RF/Microwave EDA Software Design Flow Considerations for PA MMIC Design

AWR published a new white paper about the design flow and its essential features for most PA design projects. The article presents a design of a simple, Class A GaAs pHEMT monolithic microwave integrated circuit (MMIC) PA using AWR’s Microwave Office high-frequency design software. The title of the technical paper is RF/Microwave EDA Software Design Flow Considerations for PA MMIC Design.

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Application Note: Improved Circuit Design Flow using Modelithics Passive Models

Improved Circuit Design Flow using Modelithics Passive Models

AWR released an application note about the benefits of combining Modelithics Global Models for passive RLC components with AWR’s Microwave Office high-frequency design software. The improved design flow solution maps the impact that individual components have on sub-system performance such that trade-offs can be made with regard to component values and tolerance, enabling lower manufacturing costs and improved yield. The title of the technical paper is: Improved Circuit Design Flow using Modelithics Passive Models.

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AWR Publishes Application Notes on Antenna Design

Design of a Near Field Communication Antenna System app note

AWR recently published two two application notes about antenna design. The titles of the two papers are: Design of a Near Field Communication Antenna System and Design Flow for Base Station Antennas. The NFC application note describes a sample Rohde & Schwarz NFC design using Microwave Office/AXIEM. The base station antennas article describes how antennas designed in Antenna Magus can be exported as models to AWR’s Microwave Office/AXIEM software for analysis and integration with circuits and other system components.

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USPTO Awards Patent to ClioSoft for Universal Data Management Adaptor

The US Patent & Trademark Office has approved a patent submitted by ClioSoft. The patent (US 7,975,247 B2) is for a method and system for organizing data generated by electronic design automation tools. Their patented technology is featured in their Universal Data Management Adaptor (UDMA).

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Design Flow for Heterogeneous 3D Stacked ICs

Atrenta and imec teamed together to develop an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs. 3D stacked ICs feature reduced footprint with shorter and faster interconnects, increased system integration at a lower cost, and higher modularity and reuse. 3D stacked ICs are ideal for mobile and high-performance applications, imagers, stacked DRAM, and solid-state drives.

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HHNEC-Synopsys 130nm Reference Flow 3.0

Synopsys and Shanghai Hua Hong NEC Electronics Company teamed on a 130-nanomter (nm) reference flow. The HHNEC-Synopsys Reference Flow 3.0 features the Synopsys Eclypse Low Power Solution. The reference design flow is available now from HHNEC. With the latest foundry flow, designers can leverage Synopsys’s strength in low power design and HHNEC’s manufacturing expertise.

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Cadence Enhanced Unified Custom Analog Flow

Cadence Design Systems has enhanced their Virtuoso-based custom/analog flow. The expanded custom/analog flow helps designers manage design parasitics, a DFM capability integrated within the Virtuoso environment, and the integrated Virtuoso Power System. The new features increase productivity across the entire flow from initial design specification to final GDSII and for process nodes down to 20 nanometers. The custom analog flow includes Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation technologies, Virtuoso Layout Suite, Virtuoso Power System, and Virtuoso DFM.

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Fujitsu ASIC Flow Supports Cadence C-to-Silicon Compiler

Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, announced that Fujitsu Semiconductor Limited now supports the Cadence C-to-Silicon Compiler for high-level synthesis in ASIC design flows. C-to-Silicon Compiler is the only high-level synthesis tool that embeds production RTL synthesis–Cadence Encounter RTL Compiler–to generate implementation-ready RTL for the target application. This delivers a predictable flow from transaction-level model (TLM) to GDSII, with the ability to apply ECO patches throughout, effectively reducing System Realization time. A separate Fujitsu subsidiary has already begun using C-to-Silicon Compiler in production on a large-scale design.

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Atrenta, TSMC Team on Synthesizable IP for SpyGlass Platform

Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, disclosed details of a collaboration with TSMC to enhance the quality of delivered synthesizable IP using Atrenta’s SpyGlass® platform. SpyGlass is Atrenta’s register transfer level (RTL) analysis and optimization product suite that analyzes and optimizes the quality of integrated circuit designs early in the design process, before expensive and time-consuming physical implementation begins.

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Oasys RealTime Designer Supports SystemVerilog

Oasys Design Systems announced that it has added support for SystemVerilog to RealTime Designer[tm], its revolutionary new Chip Synthesis[tm] platform used in production flows at leading-edge semiconductor and systems companies worldwide. “We are pleased and proud to have added System Verilog support within one year of delivering VHDL,” states Paul van Besouw, Oasys’ president and chief executive officer. “Design teams employing RealTime Designer are at the cutting edge of design and are increasingly using System Verilog.”

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