Cadence Design Systems’ design IP portfolio now includes intellectual property for the LPDDR3 mobile memory standard. As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption. In addition to LPDDR3, Cadence offers IP for other mobile and non-mobile memory standards in high demand by SoC designers, including Wide I/O and DDR4.
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and GLOBALFOUNDRIES, a leading provider of advanced semiconductor technology and manufacturing services, announced an agreement to develop the Synopsys DesignWare® SuperSpeed USB (3.0), USB 2.0, HDMI 1.4 Tx and Rx, DDR3/2, PCI Express® 2.0 and 1.1, SATA 1.5/3 Gbps and 6 Gbps, and XAUI PHY IP for GLOBALFOUNDRIES’ 28-nanometer (nm) “Gate First” High-k Metal Gate (HKMG) process technologies. The collaboration will enable mutual customers to differentiate their 28nm designs with a high-quality IP portfolio targeted at next-generation electronic system-on-chips (SoCs). The long-standing relationship between the two companies has resulted in the successful development of DesignWare PHY IP from 180-nm to 32-nm process technologies. GLOBALFOUNDRIES and Synopsys are the first to announce the development of USB, PCI Express, DDR, HDMI, SATA and XAUI PHY IP targeting 28-nm process technologies with scalability to future generations.
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that its DesignWare® SuperSpeed USB (USB 3.0) Solution including Controller and PHY IP successfully passed the USB Implementers Forum (USB-IF) SuperSpeed USB certification. To achieve certification, the IP must pass protocol, electrical, and interoperability tests for SuperSpeed USB (USB 3.0, 5 Gbps) and Hi-Speed USB (USB 2.0, 480 Mbps).
Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), revealed a new phase PHY technology for DDR SDRAM physical interfaces, delivering memory system performance up to 1066 MHz clock speeds (or DDR-2133 data rates) on 65-nanometer foundry process nodes or lower. Denali’s phase PHY technology applies a high-speed oversampling architecture paired with per-bit data capture and calibration mechanism to achieve GHz clock rates. This third-generation DDR PHY technology is delivered as a fully-synchronous design which benefits design teams with the configurability needed to satisfy their physical implementation requirements.
NEC Electronics (TSE: 6723) announced the development of a new family of industrial Ethernet physical layers (PHYs) for 10Base-T and 100Base-TX/FX.
The new PHYs offer the best-in-class high-speed industrial connectivity and advanced cable diagnostics, and are optimized for existing industrial Ethernet protocols used in industrial automation products. The use of industrial Ethernet has consistently ramped up in recent years and now has a wider use in automation systems throughout the industry. NEC Electronics’ new PHYs address the expansive and unique needs of system designers in the industrial automation market to interconnect industrial controllers from different manufacturers throughout a process plant.
MoSys, Inc., a leading supplier of differentiated high density embedded memory and high data rate parallel and serial interface IP, announced the availability of its PCI Express 2.0 PHY. MoSys’ PHY complies with the PIPE 2.0 specification and provides the physical layer (PHY) interface that connects to industry standard PCI Express 2.0 controllers.