Tag Archives: MIPS32

MIPS Technologies Debuts Release 5 of MIPS Architecture

MIPS Technologies ~ Release 5 (R5) of the MIPS architecture

MIPS Technologies introduced Release 5 (R5) of the MIPS architecture. R5 encompasses the MIPS32, MIPS64 and microMIPS instruction set architectures. The release incorporates important functionality including virtualization and SIMD (Single Instruction Multiple Data) modules. Key features of the MIPS architecture R5 specification are available for licensing now. Several MIPS licensees already have products in development. These features are expected to be added to MIPS processors in the coming year.

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Magma Unveils Talus RTL-to-GDSII Reference Flow for MIPS Processor IP

Magma® Design Automation (Nasdaq: LAVA), a provider of chip design software, announced availability of a validated Talus®-based RTL-to-GDSII reference flow for system-on-chip (SoC) designs that incorporate high-performance embedded microprocessor cores from MIPS Technologies, Inc. (NASDAQ: MIPS), including the MIPS32® 1004K[tm], 74K®, 34K® and 24K® families. With this reference flow and the MIPS® IP, mutual customers can achieve repeatable results and speed deployment of advanced SoCs.

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MIPS Supports Symmetric Multiprocessing on Android Platform

MIPS Technologies, Inc. (NASDAQ: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, announced symmetric multiprocessing (SMP) support for the Android[TM] platform running on MIPS-Based[TM] multicore SoCs. Now MIPS licensees using MIPS32® multi-threaded and multiprocessor cores can bring rich web and multimedia content to smartphones with the Android platform.

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Imperas Creates Models for MIPS32 M14K, M14Kc Processor Cores

Imperas released models of the new MIPS32® M14K[tm] and M14Kc[tm] processor cores from MIPS Technologies, Inc., including example virtual platforms utilizing these cores and support for the cores in Imperas’ advanced software development tools. The M14K family of processors is the first to support the new microMIPS code compression instruction set architecture (ISA) from MIPS Technologies, which is fully supported in the Imperas models. MIPS Technologies has verified the functionality of these models under the MIPS-Verified[tm] program.

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MIPS Technologies, Virage Logic Optimize Embedded Memory IP

MIPS Technologies (Nasdaq: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, and Virage Logic Corporation (Nasdaq: VIRL), the semiconductor industry’s trusted IP partner, announced they are teaming to offer optimized embedded memory IP for joint customers. With SRAM memory instances from the Virage Logic ASAP[TM] 90nm and SiWare[TM] 65GP High Density SRAM compiler families specifically optimized for MIPS32® processors, customers can speed development of complex SoCs targeted for Blu-ray DVD, HDTV, IPTV, set-top box and broadband customer premises equipment (CPE) devices.

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MIPS Technologies, Tensilica Speed SOC Design on Android Platform

MIPS Technologies, Inc. (Nasdaq: MIPS) and Tensilica® Inc. announced they are working together to accelerate SOC (system-on-chip) design activity on the popular Android platform. Together, MIPS and Tensilica will help companies speed the design of new home entertainment and mobile consumer products based on Android. A joint demo of a MIPS32® processor core integrated with Tensilica’s HiFi 2 Audio DSP will be on display in suites that both companies have at the Consumer Electronics Show in Las Vegas, January 7-10, 2010.

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