The DFI 3.1 specification was released by the DDR PHY Interface (DFI) Group. The DFI industry specification defines an interface protocol between DDR memory controllers and PHYs. The DDR PHY Interface specification enables the development of systems-on-chip (SoCs) that support the DDR3 and DDR4 memory standards. The preliminary DFI 3.1 memory specification is available now for download.
Cadence Design Systems’ design IP portfolio now includes intellectual property for the LPDDR3 mobile memory standard. As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption. In addition to LPDDR3, Cadence offers IP for other mobile and non-mobile memory standards in high demand by SoC designers, including Wide I/O and DDR4.