Cadence Design Systems’ design IP portfolio now includes intellectual property for the LPDDR3 mobile memory standard. As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption. In addition to LPDDR3, Cadence offers IP for other mobile and non-mobile memory standards in high demand by SoC designers, including Wide I/O and DDR4.
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced the availability of the high-performance DesignWare® Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards. The DesignWare Universal Memory Controller helps reduce both the latency and silicon area by up to 50 percent compared to Synopsys’ previous generations of DDR memory controllers thus improving the DRAM interface performance and reducing overall chip costs.