Tag Archives: IP

Cadence, ARM Team on Cortex-A57 64-bit Processor for TSMC 16nm FinFET Process

ARM and Cadence Design Systems teamed on the first ARM Cortex-A57 processor for TSMC’s 16-nanometer (nm) FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros. Their joint innovations will enable engineers to accelerate product development cycles and take advantage of leading-edge processes and IP.

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Cadence Design Systems Acquires Cosmic Circuits, Broadens IP Portfolio

Cosmic Circuits

Cadence Design Systems has acquire Cosmic Circuits. The IC and Systems business of Cosmic Circuits will be spun off into a separate new company to be owned by certain existing shareholders of Cosmic Circuits. The acquisition is expected to close in 30 to 60 days, and is not expected to have a material impact on Cadence’s 2013 results of operations. Terms of the transaction were not disclosed.

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Kilopass Technology Debuts Gusto-2 Non-volatile Memory IP for Instant-On Mobile Devices

Kilopass Technology launched their Gusto-2 non-volatile memory IP, which is a next generation code storage product for system-on-chip (SoC) designs for instant-on mobile devices. Gusto-2 will be available for SoC designs in the first quarter of next year. It will initially be enabled on the 55nm and 65nm logic processes at IDMs and mainstream pure play foundries with enablement on smaller process nodes following.

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Suprema Introduces FaceStation Face Recognition Terminal

Suprema FaceStation face recognition terminal

Suprema introduced their FaceStation face recognition terminal. FaceStation is an IP based biometric access control terminal. It features facial recognition technology that identifies individuals from their facial image features. FaceStation is the fastest face recognition access control terminal with patented adaptive IR illumination technology. Suprema is a provider of biometric technology and identity management solutions.

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Cadence Announces LPDDR3 Memory IP Solution

Cadence Design Systems’ design IP portfolio now includes intellectual property for the LPDDR3 mobile memory standard. As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption. In addition to LPDDR3, Cadence offers IP for other mobile and non-mobile memory standards in high demand by SoC designers, including Wide I/O and DDR4.

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Synopsys, Arteris Team on IP Solution for MIPI Alliance Low Latency Interface

Synopsys and Arteris recently teamed on a joint analog and digital IP solution to implement the MIPI Alliance Low Latency Interface (LLI) 1.0 specification. The early integration and availability of the Arteris and Synopsys solution helps speed time to market for MIPI LLI adopters. Arteris and Synopsys’ joint MIPI LLI IP solution is available now for select early access customers. System hardware implementing the joint solution will be available in the second half of 2012.

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SMIC Introduces UHD Library for 0.11um Copper Back End of Line Process

Semiconductor Manufacturing International Corporation (SMIC) introduced an ultra high density (UHD) library solution for their 0.11um Cu-BEoL (Copper Back End of Line) manufacturing platform, which can reduce chip size by an average of 31%. SMIC’s 0.11um ultra high density IP solution helps companies lower manufacturing costs and increase market competitiveness.

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Uniquify Solves Dynamic Variation Problems with Dynamic Self-Calibrating Logic

Uniquify has extended its patented self-calibrating logic (SCL) IP for double data rate (DDR) memory subsystems to solve dynamic variation problems during system operation. Dynamic Self-Calibrating Logic (DSCL) provides real-time calibration to accommodate dynamic variations in the system operating environment. Uniquify’s SCL and DSCL technologies now are included in all of their DDR memory controller IP offerings. This includes DDR1, DDR2, DDR3, DDR2/3, LPDDR1 and LPDDR2 phy and controller IP.

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Synopsys DRA Decoder for DesignWare ARC Sound Audio Processors

Synopsys introduced an optimized version of the Dynamic Resolution Adaptation (DRA) decoder software for the DesignWare ARC Sound AS211SFX and AS221BD audio processors. The DesignWare ARC Sound DRA codec and the DesignWare ARC Sound audio processors enable OEMs and SoC designer to develop HD audio for Chinese consumer electronic products. The optimized version of the DesignWare ARC Sound DRA decoder will be generally available in July 2011 (available for early access customers now).

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