ASSET InterTech published a new eBook. The publication explains how to test DDR memory with non-intrusive JTAG or boundary-scan (IEEE 1149.1) methods. The title of the paper is Testing DDR3 Memory Boundary Scan JTAG. The paper was written by Kent Zetterberg, product manager, ASSET InterTech.
ASSET InterTech published an ebook about JTAG. The article describes how the structural test methodology based on the IEEE 1149.1 boundary scan standard can apply functional tests to I2C and SPI system monitors during prototype board bring-up and later during production of the circuit board. The title of the technical paper is: Functional Test on I2C and SPI System Monitors with JTAG.