Researchers have made significant advances in post-epitaxial growth backside clean processing. The research will prepare III-V technology for high-volume manufacturing. The research leading to these accomplishments was conducted at SEMATECH’s facilities at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York.
ASSET InterTech published an ebook about the defects caused by process variances and how they can be detected with minimum effects on the manufacturing line. Manufacturing variances can degrade serdes performance and are all too common. Now embedded instrumentation offers a number of solutions for detecting process variances with minimal impact on product throughput. The title of the ebook is: How to avoid poor serdes performance caused by circuit board manufacturing variances.