Tag Archives: Design

RF Electronics: Design and Simulation eBook

AWR recently published a new eBook. The book describes the use of AWR’s Microwave Office and AXIEM software to design RF electronic devices for applications such as amplifiers, radar, mobile phones, Bluetooth, and WLAN. It was written by C. J. (Keith) Kikkert, an adjunct associate professor of James Cook University (JCU) School of Engineering and Physical Sciences, Townsville, Queensland, Australia. The title of the publication is RF Electronics: Design and Simulation.

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AWR Publishes Application Notes on Antenna Design

Design of a Near Field Communication Antenna System app note

AWR recently published two two application notes about antenna design. The titles of the two papers are: Design of a Near Field Communication Antenna System and Design Flow for Base Station Antennas. The NFC application note describes a sample Rohde & Schwarz NFC design using Microwave Office/AXIEM. The base station antennas article describes how antennas designed in Antenna Magus can be exported as models to AWR’s Microwave Office/AXIEM software for analysis and integration with circuits and other system components.

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Cadence Design Systems Buys Sigrity for $80 Million

Cadence Design Systems has acquired Sigrity for about $80 million. Sigrity develops and supports advanced software analysis solutions to ensure power integrity and signal integrity in chips, packages and printed circuit boards; and physical design tools for single die and SiP implementations. Cadence will offer Sigrity technologies immediately as add-on options to Cadence Allegro and OrCAD PCB and IC Packaging tools. The company will also continue to support Sigrity technologies used with third-party design software.

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Cadence Announces LPDDR3 Memory IP Solution

Cadence Design Systems’ design IP portfolio now includes intellectual property for the LPDDR3 mobile memory standard. As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption. In addition to LPDDR3, Cadence offers IP for other mobile and non-mobile memory standards in high demand by SoC designers, including Wide I/O and DDR4.

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White Paper: Reflective Memory Optimization Realized Through Best Practices in Design

GE Intelligent Platforms recently published a white paper on Reflective Memory (RFM) networks. The technical paper coincides with the launched of two their new products, the PCIE-5565PIORC low-profile PCIe node card and HUB-5595 DIN rail-mount hub. The title of the white paper is: Reflective Memory Optimization Realized Through Best Practices in Design.

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Synopsys CODE V 10.3 Optical Design and Analysis Software

Synopsys introduced version 10.3 of their CODE V optical design and analysis software. CODE V is an optical engineering and design software. It is used for the optimization, analysis, and tolerancing of image-forming optical systems and free-space photonic devices. CODE V 10.3 features new aspheric design tools. Aspheric surface shapes are used to help reduce or eliminate imperfect or blurred images in optical systems. An aspheric lens can be used to replace multiple spherical lenses. The CODE V 10.3 is available now.

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X-FAB Design for Reliability Webinar

X-FAB Silicon Foundries will host a webinar titled, Design for Reliability – How Process and Design Work Together to Enable Robust Technologies. The one-hour webcast will provide an overview of the underlying physics of reliability issues. The online seminar is ideal for anyone that wants to learn about the underlying physics of reliability issues and anyone involved in analog/mixed-signal design with a focus on optimizing for reliability and robustness. The event will take place on Thursday, March 3, 2011.

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Reach Technology Publishes Embedded Touch Screen Handbook

Reach Technology Inc.Reach Technology Inc., a recognized leader in Embedded Touch Screens, announced the release of an Embedded Touch Screen Handbook for medical and industrial companies seeing the value – maybe the necessity – of touch screen technology. The Embedded Touch Screen Handbook is for embedded engineers who are thinking of adding a touch screen to their product and whose main area of expertise is not LCD technology. The Embedded Touch Screen Handbook covers what is involved in adding an embedded touch screen to a product, outlines the risks (both known and hidden) involved in LCD technology.

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Chip Path Design Systems Targets Architecture Tools for ASIC, FPGA, ASSP

Chip Path Design Systems announced its formation from Parallel Engines Corporation. Chip Path is focusing on a new set of Semiconductor-IP based Architecture tools for ASIC, FPGA and ASSP design. The company has developed a new “One Architecture” specification system that allows a single architecture to be mapped onto multiple implementation platforms. Company labels this approach “Semantic-IC Design,” following in Web 3.0 nomenclature.

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