ASSET InterTech published a new eBook. The publication discusses how hardware-assisted debugging tools are able to tap into the embedded trace resources in Intel processors to methodically and quickly track bugs through the interrelated web of software, firmware and hardware. The title of the paper is: Faster Firmware Debug with Intel Embedded Trace Tools.
ASSET InterTech published a new ebook: How to Debug Dead Boards in Production. The new publication is a case study that will help circuit board manufacturers who want to recover their investment in assembled boards that won’t boot so called dead boards and still maintain the tight production deadlines that constantly reduce the time they can spend on board debug.
ASSET InterTech published a new e-book: Cache-as-RAM for Board Bring-up of Non-booting Circuit Boards. The technical paper takes a close look at how run-control tools can employ a processor’s on-chip cache memory instead of on-board RAM memory to boot non-booting prototype circuit boards. The technical publication is available now.
Mentor Graphics Corp. (NASDQ: MENT), a leader in advanced system verification solutions, and Rohde & Schwarz, a leading supplier of electronic test and measurement equipment, announced they have collaborated to deliver a hardware-accelerated, debug platform for the verification of wireless communication Systems-on-Chip (SoCs).
ASSET® InterTech, the leading supplier of open tools for embedded instrumentation, has partnered with Flextronics, a leading electronics manufacturing services (EMS) provider, to accelerate the adoption of the new IEEE P1687 Internal JTAG (IJTAG) standard. Once it is ratified next year, the IEEE P1687 IJTAG standard will specify an industry-accepted open architecture and interfacing mechanisms for instrumentation that is embedded into semiconductor chips, simplifying the use of these embedded instruments to validate, test and debug chips, circuit boards and systems.
Mentor Graphics Corp. (Nasdaq: MENT), the leader in advanced system verification solutions, and Lauterbach GmbH, the world’s largest supplier of hardware-assisted embedded debug tools, announced they have collaborated to deliver a hardware-accelerated, software-development and debug platform for the verification of Systems-on-Chip (SoCs) and embedded systems.
pls Programmierbare Logik & Systeme now also supports the 32-bit microcontroller TC1782 – the latest member of Infineon’s TriCore family AUDO Max – with its modular components based Universal Debug Engine (UDE) 2.6, the Universal Access Device 2 (UAD2) family and the Universal Emulation Configurator (UEC). pls will present these new versions for the first time at embedded world 2010 in Hall 10, Booth 10-215.
IEEE, the world’s leading professional association for the advancement of technology, announced the ratification of IEEE 1149.7 test and debug standard. The new standard expands and improves upon IEEE 1149.1 (JTAG) functionality and is designed to maximize space and cost-savings while maintaining previously made industry investments.
Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry’s trusted IP partner, announced it has added a new member, STAR[tm] (self test and repair) Silicon Browser, to its flagship STAR[tm] Memory System product family. The STAR Silicon Browser is a powerful solution to increase the efficiency of post silicon bring up, system debug and embedded memory characterization. STAR Silicon Browser provides STAR Memory System users with direct access and interactive communication with the internal circuitry of their System-on-Chip (SoC) memory system, whether it is an internally developed or third-party memory, so they can debug and diagnose system issues more quickly during the chip bring-up process. This enables the system engineer to accelerate system bring-up which is very difficult to accomplish using production ATE equipment.