Cadence Design Systems acquired Tensilica for about $380 million in cash. Tensilica is a leader in dataplane processor IP core licensing with over 200 licensees. Tensilica’s configurable dataplane processing units are optimized for embedded data and signal processing. The IP cores are ideal for mobile wireless, network infrastructure, auto infotainment and home applications. As of December 31, 2012, Tensilica had approximately $30 million in cash.
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced that, with the assistance of Fujitsu Semiconductor Limited and Fujitsu VLSI Limited (hereafter collectively called Fujitsu), Cadence has developed a standardized die model that provides ASIC and microcontroller (MCU) designers with a comprehensive chip-package-board co-design solution.
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced that STMicroelectronics, a global leader in integrated circuits for communications, consumer, computer, automotive and industrial applications, has standardized on Cadence® QRC Extraction for their 40-nanometer custom/analog designs. A key component of the Cadence digital and analog/mixed signal design flow, QRC Extraction enables faster turnaround time, scalability through its multi-core backplane, increased accuracy to silicon and capabilities to address the needs for advanced layout parasitic extraction in leading-edge technology node design.
AWR® Corporation, the innovation leader in high-frequency EDA, announced AWR Connected[tm] for Cadence® Allegro®, which enables PCB and RF co-design, simplifying the design process for high performance printed circuit board (PCB) design and significantly shortening cycle times. AWR Connected for Cadence Allegro is an interface between Cadence’s Allegro products, including both Allegro PCB and Allegro package/SiP design tools, and AWR’s Microwave Office® design software.
Duolog Technologies, the award-winning developer of IP and SoC integration products, announced that its Socrates Chip Integration Hub supports key elements of the EDA360 vision recently unveiled by Cadence. EDA360 cites the growing need for an “Open Integration Platform” to improve productivity and profitability through integration of hardware and software development activities, accelerated software development, improved IP integration, IP reuse and open standards. The Socrates Chip Integration Hub is a standards-based IP integration platform that addresses these issues by raising the level of abstraction at which IP is handled, centralizing and synchronizing design and IP metadata and automating many of the steps involved in the creation of virtual prototypes, FPGAs and SoCs.
Cadence Design Systems, Inc. (NASDAQ: CDNS), the global leader in EDA360, announced a joint development agreement with IBM to create high-performance integration-optimized IP that will help customers deliver leading-edge designs while reducing the risk and time associated with integrating complex SoC Designs. Under the agreement, the companies will develop DDR PHYs, memory controllers, and protocols such as PCIe and Ethernet under 32-nanometer silicon-on-insulator. The technology will be used in servers, video games and other devices and will be available through the newly announced Cadence® Open Integration Platform.
Cadence Design Systems, Inc. (NASDAQ: CDNS), the global leader in EDA360, announced that VIA Technology’s microprocessor subsidiary, Centaur Technology, achieved significant quality and time-to-market benefits by using the Cadence® Virtuoso® Space-Based Router on its latest set of processors. Centaur used the Cadence router to help design its new 65-nanometer Nano 3000 Series processors, designed to bring enhanced digital media performance and lower power consumption to Windows 7 notebook and desktop PC markets. Centaur adopted the Space-Based Router for 65-nanometer custom datapath designs and standard cell routing.
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that STMicroelectronics, a global leader in integrated circuits for communications, consumer, computer, automotive and industrial applications, has selected Cadence® OrCAD® PSpice® technology to provide simulation capabilities to its customers to evaluate the company’s analog and power IC’s.
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that Rohde & Schwarz, a market leader in complex RF test and measurement products, improved the quality and functionality of its complex RF integrated circuits (RFICs) through an increased simulation depth using Cadence® Virtuoso® Accelerated Parallel Simulator (APS).
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, said that Renesas Technology Corp. used the Cadence® Encounter® Digital Implementation (EDI) System and Encounter Conformal Low Power to layout a large-scale consumer system on chip (SoC) of over 8 million instances in one-half the time previously possible. Cadence Encounter technology contributed significant improvements in design time and time to market for Renesas.