Cadence Design Systems plans to acquire the IP business of Evatronix SA SKA. The acquisition is expected to close in the second quarter of 2013, and is not expected to have a material impact on Cadence’s balance sheet or second quarter or fiscal 2013 results of operations. Terms of the transaction were not disclosed.
ARM and Cadence Design Systems teamed on the first ARM Cortex-A57 processor for TSMC’s 16-nanometer (nm) FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros. Their joint innovations will enable engineers to accelerate product development cycles and take advantage of leading-edge processes and IP.
Cadence Design Systems has acquire Cosmic Circuits. The IC and Systems business of Cosmic Circuits will be spun off into a separate new company to be owned by certain existing shareholders of Cosmic Circuits. The acquisition is expected to close in 30 to 60 days, and is not expected to have a material impact on Cadence’s 2013 results of operations. Terms of the transaction were not disclosed.
Cadence Design Systems has issued a call for papers for the CDNLive Silicon Valley 2013 Users Conference. Cadence is seeking presentations and papers on design topics that illustrate users’ experiences with Cadence products, solutions, flows, methodologies, and techniques. The deadline for paper submission is December 4, 2012. Selected papers will be presented at CDNLive Silicon Valley. The event runs March 12-13, 2013 at the Hyatt Regency in Santa Clara, California.
Cadence Design Systems has acquired Sigrity for about $80 million. Sigrity develops and supports advanced software analysis solutions to ensure power integrity and signal integrity in chips, packages and printed circuit boards; and physical design tools for single die and SiP implementations. Cadence will offer Sigrity technologies immediately as add-on options to Cadence Allegro and OrCAD PCB and IC Packaging tools. The company will also continue to support Sigrity technologies used with third-party design software.
The DFI 3.1 specification was released by the DDR PHY Interface (DFI) Group. The DFI industry specification defines an interface protocol between DDR memory controllers and PHYs. The DDR PHY Interface specification enables the development of systems-on-chip (SoCs) that support the DDR3 and DDR4 memory standards. The preliminary DFI 3.1 memory specification is available now for download.
Cadence Design Systems introduced a new full-featured NVM Express interface subsystem. It is the industry’s first IP subsystem for the development of SoCs that support the NVM Express 1.0c standard, which is an interface technology used for solid-state drives (SSD). With Cadence’s IP subsystem, SoC designers do not need to source their interface component IP separately and drive integration on their own. The new subsystem approach decreases design risk and overall development time for new SoCs.
The Cadence Verification IP (VIP) Catalog now supports the 12Gb/s SAS and NVM Express protocol standards used in cloud computing applications. By doubling the data transfer rate, 12Gb/s SAS improves the cost performance density of SAS interconnects and enables higher degrees of capacity scaling. Pre-silicon verification capabilities, such as those offered by Cadence Design Systems with their VIP products, are critical to the SAS ecosystem and reinforce the interoperability required of these pervasive storage interconnects.
Cadence Design Systems’ design IP portfolio now includes intellectual property for the LPDDR3 mobile memory standard. As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption. In addition to LPDDR3, Cadence offers IP for other mobile and non-mobile memory standards in high demand by SoC designers, including Wide I/O and DDR4.
Cadence Design Systems has issued a call for papers for their 2012 CDNLive! Users Conference. Papers considered should address new technologies and methodologies for realizing next generation systems, silicon, and differentiated IP. The deadline to submit a paper is November 11, 2011. The CDNLive! Users Conference helps design engineers stay on the competitive edge by sharing knowledge with top designers and executives. The event will take place March 13-14, 2012 in San Jose, California.