Tag Archives: ASSET InterTech

eBook: Faster Firmware Debug with Intel Embedded Trace Tools

Faster Firmware Debug with Intel Embedded Trace Tools eBook | ASSET InterTech

ASSET InterTech published a new eBook. The publication discusses how hardware-assisted debugging tools are able to tap into the embedded trace resources in Intel processors to methodically and quickly track bugs through the interrelated web of software, firmware and hardware. The title of the paper is: Faster Firmware Debug with Intel Embedded Trace Tools.

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New eBook: Testing DDR3 Memory Boundary Scan JTAG

Testing DDR3 Memory Boundary Scan JTAG eBook | ASSET InterTech

ASSET InterTech published a new eBook. The publication explains how to test DDR memory with non-intrusive JTAG or boundary-scan (IEEE 1149.1) methods. The title of the paper is Testing DDR3 Memory Boundary Scan JTAG. The paper was written by Kent Zetterberg, product manager, ASSET InterTech.

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How to Debug Dead Boards in Production eBook

How to Debug Dead Boards in Production eBook

ASSET InterTech published a new ebook: How to Debug Dead Boards in Production. The new publication is a case study that will help circuit board manufacturers who want to recover their investment in assembled boards that won’t boot so called dead boards and still maintain the tight production deadlines that constantly reduce the time they can spend on board debug.

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Ebook: Functional Test on I2C and SPI System Monitors with JTAG

Functional Test on I2C and SPI System Monitors with JTAG ebook

ASSET InterTech published an ebook about JTAG. The article describes how the structural test methodology based on the IEEE 1149.1 boundary scan standard can apply functional tests to I2C and SPI system monitors during prototype board bring-up and later during production of the circuit board. The title of the technical paper is: Functional Test on I2C and SPI System Monitors with JTAG.

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Cache-as-RAM for Board Bring-up of Non-booting Circuit Boards

Cache-as-RAM for Board Bring-up of Non-booting Circuit Boards

ASSET InterTech published a new e-book: Cache-as-RAM for Board Bring-up of Non-booting Circuit Boards. The technical paper takes a close look at how run-control tools can employ a processor’s on-chip cache memory instead of on-board RAM memory to boot non-booting prototype circuit boards. The technical publication is available now.

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White Paper: Solving the Problem of Diminishing Test Coverage from In-circuit Test

Solving the problem of diminishing test coverage from in-circuit test (ICT) white paper ~ ASSET InterTech

ASSET InterTech released a new white paper that explains why test coverage from intrusive, probe-based in-circuit testers with their bed-of-nails fixtures is diminishing. The technical paper is titled, Solving the problem of diminishing test coverage from in-circuit test (ICT). The ebook was written by Adam Ley, chief technologist of non-intrusive board test for ASSET.

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White Paper Explains How Increasing Bus Speeds Degrades Throughput Performance

Bandwidth tests reveal shrinking eye diagrams and signal integrity problems

ASSET InterTech published a white paper titled: Bandwidth tests reveal shrinking eye diagrams and signal integrity problems. The paper explains how increasing bus speeds on circuit boards could create havoc for signal integrity on those buses, in turn degrading the bus’ throughput performance. Each new generation of a high-speed bus typically runs at a higher signal frequency, but this decreases the margin for error on the bus, making it more sensitive to disruptions from jitter, inter-symbol interference (ISI), crosstalk and other factors.

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White Paper: How to test high-speed memory with non-intrusive embedded instruments

How to test high-speed memory with non-intrusive embedded instruments white paper

ASSET InterTech published a new white paper about non-intrusive embedded instruments. The technical paper explains how non-intrusive software-driven embedded instruments can overcome many of the challenges of testing, validating and debugging high-speed memory buses such the DDR 3 or DDR4 (DDR3/4) buses, and others. The title of their article is “How to test high-speed memory with non-intrusive embedded instruments.”

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ASSET InterTech, Flextronics Team on IEEE P1687 Internal JTAG Standard

ASSET® InterTech, the leading supplier of open tools for embedded instrumentation, has partnered with Flextronics, a leading electronics manufacturing services (EMS) provider, to accelerate the adoption of the new IEEE P1687 Internal JTAG (IJTAG) standard. Once it is ratified next year, the IEEE P1687 IJTAG standard will specify an industry-accepted open architecture and interfacing mechanisms for instrumentation that is embedded into semiconductor chips, simplifying the use of these embedded instruments to validate, test and debug chips, circuit boards and systems.

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ASSET InterTech, IPextreme Team on IEEE 1149.7 Test Solution

ASSET® InterTech, Inc., the leading supplier of open tools for embedded instrumentation, will integrate test adapter intellectual property (IP) from IPextreme into its ScanWorks® platform for embedded instruments to enable chip and circuit board tests under the new IEEE 1149.7 reduced-pin boundary scan standard. “IPextreme leads the market with the industry’s first IEEE 1149.7 synthesizable IP,” said Pierre Xavier-Thomas, vice president of engineering, IPextreme. “We are excited about working with ASSET to accelerate the availability of IEEE 1149.7 tools in the marketplace. This will enlarge the IEEE 1149.7 ecosystem and benefit end users.”

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