ARM and Cadence Design Systems teamed on the first ARM Cortex-A57 processor for TSMC’s 16-nanometer (nm) FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros. Their joint innovations will enable engineers to accelerate product development cycles and take advantage of leading-edge processes and IP.
Participants at the recent 7th Annual International Symposium on Advanced Gate Stack Technology discussed strategies for implementing advanced logic and memory technologies for sub-16 nm node and beyond process technologies. The Symposium, hosted by SEMATECH, drew more than 100 international researchers from industry and academia that shared recent discoveries and outlined new gate stack strategies for the 16nm technology generation and beyond.