Mentor Graphics T3Ster Inspires JESD51-14 Thermal Testing Standard
JEDEC has approved the JESD51-14 standard, which is titled Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction-to-case of Semiconductor Devices with Heat Flow through a Single Path. The thermal transient testing-based measurement methodology is based on an idea published jointly by the Mentor Graphics MicReD group and Infineon the Automotive Power Application group. JEDEC is an organization dedicated to open standards in the microelectronics industry.
Cadence Design Systems Expands Verification IP Catalog
Cadence Design Systems has expanded their portfolio of verification IP (VIP) and memory models for SoC, and System-level verification engineers and designers. The expanded Cadence VIP offering now supports all major third party simulators. As a result, Cadence offers designers a one-stop shop of mainstream and emerging protocols for developing and verifying advanced electronic designs.
Danaher Acquires Keithley Instruments
Keithley Instruments, Inc. (NYSE: KEI), a world leader in advanced electrical test instruments and systems, announced completion of the merger of Aegean Acquisition Corporation, an indirect wholly owned subsidiary of Danaher Corporation, into Keithley pursuant to the previously announced Merger Agreement dated September 29, 2010 among Danaher Corporation, Aegean Acquisition Corporation and Keithley. Under the terms of the merger agreement, each outstanding common share and class B common share of Keithley has been converted into the right to receive $21.60 per share, in cash, without interest. Keithley is now an indirect wholly owned subsidiary of Danaher Corporation and, as a result of the completion of the merger, Keithley shares will cease to trade on the New York Stock Exchange at the close of the market today.
IAR Embedded Workbench Supports Renesas RX Microcontrollers
IAR Systems® announced that Renesas Electronics’ RX microcontroller architecture is the next target architecture to benefit from the innovative power debugging technology included in IAR Embedded Workbench®. Using power debugging, embedded software can be developed and tuned to save power by exercising stricter control of how and when the hardware consumes power. Keeping the power consumption down extends battery lifetime in mobile applications and reduces heat dissipation.
Mentor Graphics, Rohde & Schwarz Team on Wireless SoC Debug Platform
Mentor Graphics Corp. (NASDQ: MENT), a leader in advanced system verification solutions, and Rohde & Schwarz, a leading supplier of electronic test and measurement equipment, announced they have collaborated to deliver a hardware-accelerated, debug platform for the verification of wireless communication Systems-on-Chip (SoCs).
ASSET InterTech, Flextronics Team on IEEE P1687 Internal JTAG Standard
ASSET® InterTech, the leading supplier of open tools for embedded instrumentation, has partnered with Flextronics, a leading electronics manufacturing services (EMS) provider, to accelerate the adoption of the new IEEE P1687 Internal JTAG (IJTAG) standard. Once it is ratified next year, the IEEE P1687 IJTAG standard will specify an industry-accepted open architecture and interfacing mechanisms for instrumentation that is embedded into semiconductor chips, simplifying the use of these embedded instruments to validate, test and debug chips, circuit boards and systems.
Mentor Graphics, ARM Team on Automated Memory Test and Repair
Mentor Graphics Corporation (NASDAQ: MENT) announced it has teamed up with ARM to provide an automated memory test and repair solution for ARM embedded memories and processor cores. The new capability provides full interoperability between Mentor’s industry-leading Tessent[TM] memory test and repair solution and ARM’s family of cores and embedded memory IP.
Synopsys to Expand Test Technology Embedded in RTL Synthesis
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced plans to expand test technology embedded in Synopsys’ RTL synthesis to address the need for higher defect coverage, lower test cost and faster yield analysis while simultaneously minimizing the impact on design goals and project schedules. Design teams currently using Synopsys’ RTL synthesis and test solution are able to quickly implement compression to lower digital logic test costs, handle pin-limited test methodologies and execute on-chip testing of high-speed blocks like USB and PCI Express® cores.
ASSET Announces ScanWorks DDR3 Memory Toolkit for Intel Processors
A new toolkit for ASSET’s ScanWorks® platform for embedded instruments will allow memory suppliers to thoroughly validate the connectivity of their DDR3 memory chips with certain advanced Intel® processors. ASSET® InterTech is the leading supplier of open tools for embedded instrumentation. The ScanWorks DDR3 memory toolkit will verify the performance of the bus that connects DDR3 memory devices to Intel’s processors based on the next-generation micro-architecture codenamed Sandy Bridge. ASSET and Intel have been collaborating on validation and test tools that take advantage of Intel’s embedded instrumentation technology, the Intel® Interconnect Built-In Self Test (Intel® IBIST). Intel has been placing Intel IBIST into its advanced processors and chipsets to facilitate validation, test and debug applications. ASSET’s ScanWorks platform has tools for utilizing Intel IBIST.
Silicon Image Lowers Test Cost, Time with DFTMAX Compression
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Silicon Image, Inc., a leading provider of semiconductors and IP for the secure distribution, presentation and storage of high-definition content, employed DFTMAX[tm] compression, an integral part of the Galaxy[tm] Implementation Platform, to significantly lower manufacturing test cost and time. Silicon Image’s mixed-signal multimedia design testing requirements included a tight form factor and a limited number of package pins. Using the new pin-limited test capability in Synopsys’ DFTMAX, Silicon Image designers easily implemented test compression for the mixed-signal chip in just two days, substantially reducing test time, data and cost while achieving high test coverage.
« Newer Posts || Older Posts »
If you are familiar with RSS feeds, you can also sign up for our free news feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
