'Test Solution' Category Archive

ASSET InterTech to Offer Open Tools for Embedded Instrumentation

Posted by EDA Geek News Staff in Test Solution on Wednesday, May 14, 2008

Responding to the increasing momentum in the electronics industry toward embedded instrumentation, ASSET® InterTech, Inc. announced it is positioning the company, its products and its technologies to provide open tools for embedded instrumentation in design validation, test and debug applications. Many of the established validation and test technologies are inadequate or ineffective for high-speed chips, I/O buses and systems. Moreover, new chip geometries at 45 nanometers (nm) or smaller, as well as chip-level packaging technologies like system-in-package (SiP) are making validation, test and debug very difficult, if not impossible with traditional technologies.

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IZT GmbH Introduces S5000 COMINT Stimulator

Posted by EDA Geek News Staff in Test Solution on Wednesday, May 14, 2008

Generating test signals for today's COMINT (Communication Intelligence) systems requires far more features than a standard signal generator or RF test source can offer. The IZT S5000 COMINT Stimulator is designed to simulate realistic RF spectrum usage for these systems: The product generates up to several hundred realistic signals of different bandwidth with real content. One IZT S5000 covers an instantaneous bandwidth of 120MHz anywhere in the frequency range up to 3GHz. If more signals over a larger bandwidth are required, the control software can integrate multiple IZT S5000s for continuous coverage of the spectrum with thousands of emissions.

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Renesas Adopts Teradyne J750 Platform for Final Microcontroller Test

Posted by EDA Geek News Staff in Test Solution on Monday, May 12, 2008

Teradyne, Inc. (NYSE: TER) announced Renesas Technology Corp. has standardized their microcontroller final test using the J750 Platform of test systems in Renesas Semiconductor (Beijing) Co., Ltd. Renesas, a joint venture of Hitachi, Ltd. and Mitsubishi Electric Corporation formed in 2003, currently uses the J750 Platform for volume production in China and Japan. The standardization of the J750 Platform will add to a multitude of Teradyne systems the companies have purchased for various test applications since 1973. Renesas will use the J750 Platform to test microcontrollers used in automotive, consumer, communication and industrial applications.

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JTAG Technologies to Launch New Products at National Electronics Week

Posted by EDA Geek News Staff in Test Solution on Monday, May 12, 2008

JTAG Technologies, the acknowledged market leader in IEEE Std 1149 boundary-scan tools, will be using the National Electronics Week (17th to 19th June, at Earls Court, London) to unveil a number of new product developments, including enhancements to its popular test development tool ProVision. New hardware to simplify JTAG boundary-scan integration into a number of proprietary test systems will also be debuted on JTAG Technologies stand (C21) at NEW.

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CWAV Announces USBee PacketPresenter Graphical Protocol Decoder

Posted by EDA Geek News Staff in Test Solution on Friday, May 9, 2008

CWAV Inc., a Southern California-based electronics company, announced significant enhancements for its USBee DX Logic Analyzer / Oscilloscope by adding the PacketPresenter[tm] Protocol Decoder to its suite of electronics debugging tools. The PacketPresenter decodes and displays bus traffic that is captured by the USBee DX Logic Analyzer in a graphical, easy to understand packet format. The PacketPresenter packetizes the raw bus data, removes encoding, parses it into fields and displays it in a customizable format, going far beyond simple bus decoders that only output byte values.

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Elma, DFT Microsystems Team on SerDes Test Modules for Embedded Systems

Posted by EDA Geek News Staff in Test Solution on Wednesday, May 7, 2008

Elma Electronic Inc., a global manufacturer of electronic packaging products, and DFT Microsystems, a leader in high density test solutions for high-speed semiconductor device interfaces, have partnered to offer high-speed SerDes Test modules for the embedded systems market. The first Test module the companies are releasing is the DV3200, designed for the VPX architecture. It is fully compliant to the latest VITA 46.0 base specification and comes in the 6U form factor. The modules can be used to test the true Bit Error Rate (BER) performance for the multi-gigabit per second signals across the serial links. Jitter, timing, voltage, and pattern tests can be generated with the DV3200.

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