Cadence Design Systems introduced a new full-featured NVM Express interface subsystem. It is the industry’s first IP subsystem for the development of SoCs that support the NVM Express 1.0c standard, which is an interface technology used for solid-state drives (SSD). With Cadence’s IP subsystem, SoC designers do not need to source their interface component IP separately and drive integration on their own. The new subsystem approach decreases design risk and overall development time for new SoCs.
Uniquify has extended its patented self-calibrating logic (SCL) IP for double data rate (DDR) memory subsystems to solve dynamic variation problems during system operation. Dynamic Self-Calibrating Logic (DSCL) provides real-time calibration to accommodate dynamic variations in the system operating environment. Uniquify’s SCL and DSCL technologies now are included in all of their DDR memory controller IP offerings. This includes DDR1, DDR2, DDR3, DDR2/3, LPDDR1 and LPDDR2 phy and controller IP.
The new ARMv8 architecture will feature a 64-bit instruction set. The ARMv8 architecture will expand the reach of ARM processor-based solutions into consumer and enterprise applications where extended virtual addressing and 64-bit data processing are required. The ARMv8 architecture specifications describing all aspects of the ARMv8 architecture are available now to partners under license. ARM will disclose processors based on ARMv8 during 2012, with consumer and enterprise prototype systems expected in 2014.
Kilopass Technology introduced their Itera embedded multi-time programmable (MTP) NVM 40nm solution. Itera replaces external serial EEPROM and NOR flash in high-volume mobile and consumer applications. Itera reduces costs (70% less), increases performance (24X increase), and improves integration. The pricing of Itera is based on percentage of cost savings over external EEPROM and NOR Flash solutions. There are two pricing components: (1) license fee for use of Itera in a design and (2) a per wafer royalty. Itera is available in MTP capacity from 32 bit to 1Mb. It is now available at foundries like TSMC, GLOBALFOUNDRIES, and UMC in 40nm bulk silicon with 65nm and 55nm in H2’11.
Synopsys introduced their DesignWare Data Converter IP solutions. The DesignWare Data Converter IP solutions are available now for the 65-nm LP process. Support for the 40-nm LP process will be available in the second quarter. DesignWare data converters for broadband communication applications are also available now in the 65-nm LP and 40-nm LP processes. The Synopsys IP solutions are optimized for mobile broadband wireless communication applications like WiFi, WiMAX, LTE, and digital TV reception.
MIPS Technologies, Inc. (Nasdaq: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, announced it is working with leading providers of key IP for the connected digital home-including audio, video, graphics and security functionality-to help SoC developers get to market quickly with fully-integrated hardware/software solutions. MIPS is working closely with Chips & Media, Discretix, Tensilica, Vivante Corp. and other leading providers of semiconductor IP to help customers meet cost/performance targets with solutions that optimize performance for devices based in particular on the Android platform.
GDA Technologies, Inc., a leading supplier of configurable, reliable and production-proven Intellectual Property (IP) solutions for communication, storage and consumer markets, has announced that it is adding IBM’s PowerPC 440T90 to its existing 405S and 460S products using TSMC 90nm process technology. Customers can take advantage of this “hardened processor” that is optimized for performance, low power dissipation and optimized die size. This gives additional dimension to GDA’s expertise in developing SoC’s utilizing Power Architecture(R).
Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), revealed a new phase PHY technology for DDR SDRAM physical interfaces, delivering memory system performance up to 1066 MHz clock speeds (or DDR-2133 data rates) on 65-nanometer foundry process nodes or lower. Denali’s phase PHY technology applies a high-speed oversampling architecture paired with per-bit data capture and calibration mechanism to achieve GHz clock rates. This third-generation DDR PHY technology is delivered as a fully-synchronous design which benefits design teams with the configurability needed to satisfy their physical implementation requirements.
Broadcom Corporation (Nasdaq: BRCM), a global leader in semiconductors for wired and wireless communications, announced that it is offering its BroadVoice family of voice codecs royalty-free and without any licensing fees. As a direct response to customer demand for advanced, high-quality voice solutions and development tools, Broadcom is releasing its wideband and narrowband BroadVoice codecs in both floating-point and fixed-point C code as open source software under the GNU Lesser General Public License (LGPL), version 2.1, as published by the Free Software Foundation.
Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry’s trusted IP partner, announced it has qualified its AEON® non-volatile memory (NVM) solution on TSMC’s 65-nanometer (nm) Low Power (LP) process. As the industry’s first multi-time programmable (MTP) logic NVM solution that is commercially available on a 65nm process, AEON further extends Virage Logic’s NVM provider leadership position.