STARC STARCAD-CEL 2.0 Flow Features FishTail Focus, Confirm Tools
FishTail Design Automation, Inc., the golden timing constraints company, announced that Japan's Semiconductor Technology Academic Research Center (STARC) has released a new production flow for chip implementation using FishTail's technology for timing exception generation and verification. The STARCAD-CEL Version 2.0 flow includes the use of FishTail products Focus(tm) and Confirm(tm) to generate and verify false and multi-cycle paths on complex SoC designs.
IMEC Introduces Variability Aware Modeling Flow for Sub-45nm
IMEC reports a variability-aware modeling (VAM) flow that analyzes process variability of sub-45nm technologies which enables designers to optimize their system design for timing, energy and yield versus expected application load. The flow assesses the impact of process variations and degradation effects of sub-45nm technologies on the system performance by giving valuable information to the designer. IMEC's VAM flow can hook into commercial design for manufacturing (DFM) tools and has been validated on industrial process technology data and IP cores.
Tela Innovations Shares Vision for Design Solution at 45nm and Beyond
Tela Innovations, an early-stage technology company focused on addressing the challenges of scaling semiconductor manufacturing to 45nm and beyond, unveiled its business strategy and technology vision for using on-grid, straight-line, one-dimensional layout structures to provide a more efficient and reliable way to design and manufacture next generation chips. Details of the solution were disclosed at the SPIE Advanced Lithography Conference in joint presentations from Tela and ASML/Brion and Applied Materials.
Mentor, Calypto Team on Integrated Catapult C, SLEC Design Flow
Mentor Graphics Corporation (NASDAQ:MENT) announced the availability of a new electronic system level (ESL) hardware design and verfication flow featuring Mentor's Catapult® C Synthesis tool and Calypto Design Systems' SLEC sequential equivalence checker. Proven during trials at customer sites throughout the world and recently by STARC, the integrated flow is effective at synthesizing high-quality designs from pure ANSI C++ to RTL, and formally verifying that the resulting RTL design is functionally correct. These customer results validate the Mentor/Calypto design flow, and indicate its readiness for broad production usage by companies using ESL methodologies for hardware design.
Cadence, ARM Create Multicore, Low-Power Reference Methodologies
Cadence Design Systems, Inc. (NASDAQ: CDNS) and ARM [(LSE: ARM); (NASDAQ: ARMHY) announced the availability of two new implementation reference methodologies jointly developed by the companies, one for the ARM11(TM) MPCore(TM) multicore processor and the other for low-power implementation of the ARM1176JZF-S(TM) processor, which incorporates ARM® Intelligent Energy Manager (IEM(TM)) technology. These Cadence reference methodologies for the two ARM processors are the result of close collaboration between the two companies, and provide enhanced design solutions to mutual customers designing multicore, low-power devices.
Synopsys, UMC Create 65nm Multi-voltage RTL-to-GDSII Reference Flow
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, and UMC (NYSE: UMC)(TSE: 2303), a world-leading semiconductor foundry, announced the release of a 65-nanometer (nm) hierarchical, multi-voltage RTL-to-GDSII reference design flow. The flow is based on Synopsys' Galaxy(TM) Design Platform and features the IC Compiler place-and-route solution and the Design Compiler® Ultra topographical synthesis solution for comprehensive design implementation support. Key features of the reference flow include support for power management with multi-voltage design and power gating, as well as design-for-manufacturing (DFM) capabilities with the addition of critical area analysis (CAA).
If you are familiar with RSS feeds, you can also sign up for our free news feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
