'Design Flow' Category Archive

TSMC Reference Flow 9 Includes GoldTime Statistical Timing Analysis

Posted by EDA Geek News Staff in Design Flow, EDA Tools on Tuesday, June 3, 2008

Extreme DA[tm] announced that TSMC Reference Flow 9.0 covers the GoldTime[tm] Statistical timing analyzer. Supporting 40nm process technology, Reference Flow 9.0 is the latest generation of TSMC's design methodology to increase yields, lower risks, and reduce design margins. At advanced process nodes, statistical analysis software is required to analyze global and local variations, which affect integrated circuit (IC) performance. With improved analysis, design teams can design ICs with higher performance and improved robustness while reducing development efforts. Visit Extreme DA in booth 1364 at the Design Automation Conference in Anaheim, Calif., June 9 - 12.

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TSMC Announces Reference Flow 9.0

Posted by EDA Geek News Staff in Design Flow on Tuesday, June 3, 2008

Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) introduced Reference Flow 9.0, the latest version of TSMC's industry-leading design methodology to lower design obstacles, improve design margins, and increase yields of its 40nm process technology. Reference Flow 9.0 is also one of the key collaborative components of the company's recently unveiled Open Innovation Platform[tm].

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Power Flow Integrates Calypto PowerPro CG, Cadence Encounter RTL Compiler

Posted by EDA Geek News Staff in Design Flow on Thursday, May 29, 2008

Calypto[tm] Design Systems Inc., the leader in sequential analysis technology, announced the availability of an RTL power optimization flow to integrate Calypto's PowerPro CG product with the Encounter® RTL Compiler from Cadence Design Systems, Inc. The integrated flow provides an automated, single-pass sequential analysis capability that produces the lowest power implementation while still meeting design constraints.

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STARC STARCAD-CEL 2.0 Features Sequence PowerTheater, CoolTime Tools

Posted by EDA Geek News Staff in Design Flow on Monday, May 26, 2008

Sequence Design, the EDA leader in Design for Power (DFP) solutions, announced that its PowerTheater and CoolTime low-power tools have been integrated into the latest release of the Japanese Semiconductor Technology Academic Research Center (STARC) advanced design flow, STARCAD-CEL Version 2.0. STARCAD-CEL Version 2.0, addressing the challenges of very advanced process technologies including 65nm and 45nm, has been updated to emphasize low-power design, particularly RTL power analysis and reduction, and power integrity at physical implementation. The STARCAD-CEL Version 2.0 design methodology is shared by the leading Japanese semiconductor companies that comprise STARC's membership as a standard digital design platform.

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Cadence Debuts RTL to GDSII Reference Flows for ARM Cortex-A9

Posted by EDA Geek News Staff in Design Flow on Tuesday, April 29, 2008

Cadence Design Systems, Inc. (NASDAQ: CDNS) announced the immediate availability of multiple, silicon-ready RTL to GDSII implementation flows based on the Cadence® Encounter® digital IC design platform, for the ARM® Cortex(tm)-A9 processor. The flows are available for three configurations of the ARM Cortex-A9 processor: single core, dual Cortex-A9 MPCore(tm) multicore processor and quad Cortex-A9 MPCore(tm) multicore processor. Proven to enable ARM Cortex-A9 processor performance of up to 800MHz (production-margined at worst case PVT conditions), these reference methodologies offer time-to-market savings for customers designing for high performance within tight power constraints for next-generation devices such as smart phones, mobile internet devices, consumer electronics, automotive infotainment, networking and other embedded and enterprise devices.

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STARC STARCAD-CEL 2.0 Design Flow Features Atrenta Tools

Posted by EDA Geek News Staff in Design Flow on Wednesday, April 23, 2008

Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, announced the integration of its SpyGlass®, SpyGlass-Constraints, SpyGlass-DFT, SpyGlass-Power, and 1Team®-Implement products into the latest production flow from the Semiconductor Technology Academic Research Center (STARC). Called STARCAD-CEL Version 2.0, the new production flow supports RTL analysis as well as chip implementation, offering a comprehensive solution for early constraints analysis and management, design-for-test (DFT), low power design, and design feasibility analysis. The Atrenta products were proven effective in the STARCAD-CEL reference flows.

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