Category Archives: Design Flow

Cadence, ARM Team on Next Generation SoC Design Flow

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, and ARM, Ltd. [(LSE: ARM); (Nasdaq: ARMH)] announced that the two companies have entered into a strategic collaboration to create a next-generation SoC design flow that will accelerate time to market and lower the cost of SoC integration and verification. Under the terms of the agreement, the Cadence® Chip Planning System and Cadence Incisive® functional verification solutions will be combined with ARM® AMBA® Designer, Performance Exploration tools and Network Interconnect IP.

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Cadence, STARC Team on Next-Generation Analog Mixed-Signal Reference Flow

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it will collaborate with STARC to develop the Japanese electronic design consortium’s next-generation analog/mixed-signal reference flow. Cadence and STARC will use Cadence® Virtuoso® IC 6.1 technology as the platform for developing the STARCAD-AMS flow. STARC is a consortium made up of 10 electronics companies, six of whom participate in the areas of analog and mixed-signal design.

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TSMC Reference Flow 10.0 Features Mentor Graphics Low Power Solution

Mentor Graphics Corporation (NASDAQ:MENT) announced that its low power RTL-to-GDSII tool flow has been included in Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) Reference Flow 10.0. TSMC and Mentor worked together nearly a year to validate and deliver a robust set of tools with proven support for the Unified Power Format (UPF). “In addition to expanding the Mentor reference flow to add both functional verification and implementation technologies, Mentor is addressing new challenges such as low power,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.

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STARC Implements Cadence Encounter for Designs Over 20 Million Gates

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, announced that the Japanese electronic design consortium STARC is implementing a Cadence® flow for semiconductor designs larger than 20 million gates. The new STARCAD-CEL V3.0 methodology for large-scale design was defined by the consortium to describe a comprehensive, RTL-to-GDSII design methodology for quickly designing semiconductor systems of this size. After extensive evaluation, the Cadence Encounter® platform and methodology met all necessary STARC requirements.

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STARC Litho-Aware 45nm DFM Design Flow Features Cadence Encounter

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, announced the Japanese semiconductor research consortium STARC (Semiconductor Technology Academic Research Center), has integrated the Cadence® Encounter® Digital Implementation System, with its integrated DFM technologies, as its DFM flow targeting 45 nanometer designs and below. The comprehensive DFM suite integrates Cadence Litho Physical Analyzer (LPA), Cadence Litho Electrical Analyzer (LEA), and Cadence CMP Predictor into the designer’s cockpit. Using the Cadence enabled STARCAD-CEL V3.0 Ref Flow, designers gain ready access to process-accurate manufacturing information early in the physical design flow, where engineers can leverage the seamless integration in digital implementation to identify, analyze and correct yield-limiting hotspots for their advanced-node designs. In addition, with Litho Electrical Analyzer, designers can analyze the litho impact on transistor performance and make necessary design trade-offs to meet their design criteria.

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Duolog Socrates Chip Integration Platform Integrates with Arteris NoC

Arteris Inc., the leading developer of Network on Chip (NoC) solutions, and Duolog, a provider of SoC integration tools, announced the integration of Duolog design tools with Arteris’ NoC solution to provide designers a more streamlined and efficient way to integrate multiple semiconductor intellectual property (IP) blocks on a single system on chip (SoC) device. The integration leverages Arteris’ NoC solution for enabling high-performance on-chip interconnect and communications, and Duolog’s Socrates[tm] Chip Integration Platform, which is a suite of tools for capturing, viewing and validating various elements of the infrastructure of complex SoCs.

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Agilent Announces TriQuint PDK for TQPED GaSs E/D pHEMT Process

Agilent Technologies Inc. (NYSE:A) announced the availability of a powerful foundry-certified process design kit (PDK) to support TriQuint Semiconductor’s popular TQPED GaSs E/D pHEMT process. Providing the most complete MMIC design flow available using Agilent’s Advanced Design System (ADS) platform, the new TQPED PDK completely renovates layout functions, adds many design automation and routing capabilities, and provides a MMIC toolbar personality to help streamline the MMIC design process. The PDK is available now from TriQuint.

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3L Becomes Member of Texas Instruments Developer Network

3L, the Multiprocessor Design Company, announced that it has joined the Texas Instruments Incorporated (TI) Developer Network as a provider of multiprocessor design solutions. The announcement strengthens 3L’s multiprocessor design flow targeting TI digital signal processors (DSPs) and offers tighter integration between 3L’s Diamond multiprocessor tool suite and the TI portfolio of DSPs as well as Code Composer Studio (CCStudio) integrated development environment (IDE).

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Forte Announces Electronic System Level Design Flow Seminars

Forte Design Systems, a leading provider of SystemC-based High Level Synthesis software, will kick off a series of training seminars in May for semiconductor companies to better understand how to implement an electronic system level (ESL) design flow. The two-part series, scheduled to start May 11 in Korea, with additional dates in Japan, the United States and Europe throughout 2009, is designed for hardware engineers and their managers.

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Encounter Conformal Constraint Designer Qualifies for STARCAD-CEL Flow

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, announced that the Semiconductor Technology Academic Research Center (STARC) in Japan has qualified the Cadence® Encounter® Conformal® Constraint Designer for use in the STARCAD-CEL design flow for advanced semiconductor design. The qualification demonstrates that Encounter Conformal Constraint Designer has delivered production-quality results and provides a robust solution for the various requirements of multiple STARC member companies.

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