Mentor, Calypto Team on Integrated Catapult C, SLEC Design Flow
Mentor Graphics Corporation (NASDAQ:MENT) announced the availability of a new electronic system level (ESL) hardware design and verfication flow featuring Mentor's Catapult® C Synthesis tool and Calypto Design Systems' SLEC sequential equivalence checker. Proven during trials at customer sites throughout the world and recently by STARC, the integrated flow is effective at synthesizing high-quality designs from pure ANSI C++ to RTL, and formally verifying that the resulting RTL design is functionally correct. These customer results validate the Mentor/Calypto design flow, and indicate its readiness for broad production usage by companies using ESL methodologies for hardware design.
Cadence, ARM Create Multicore, Low-Power Reference Methodologies
Cadence Design Systems, Inc. (NASDAQ: CDNS) and ARM [(LSE: ARM); (NASDAQ: ARMHY) announced the availability of two new implementation reference methodologies jointly developed by the companies, one for the ARM11(TM) MPCore(TM) multicore processor and the other for low-power implementation of the ARM1176JZF-S(TM) processor, which incorporates ARM® Intelligent Energy Manager (IEM(TM)) technology. These Cadence reference methodologies for the two ARM processors are the result of close collaboration between the two companies, and provide enhanced design solutions to mutual customers designing multicore, low-power devices.
Synopsys, UMC Create 65nm Multi-voltage RTL-to-GDSII Reference Flow
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, and UMC (NYSE: UMC)(TSE: 2303), a world-leading semiconductor foundry, announced the release of a 65-nanometer (nm) hierarchical, multi-voltage RTL-to-GDSII reference design flow. The flow is based on Synopsys' Galaxy(TM) Design Platform and features the IC Compiler place-and-route solution and the Design Compiler® Ultra topographical synthesis solution for comprehensive design implementation support. Key features of the reference flow include support for power management with multi-voltage design and power gating, as well as design-for-manufacturing (DFM) capabilities with the addition of critical area analysis (CAA).
Altos Design, Extreme DA Create Statistical Design Flow for 65nm ICs
Altos Design Automation Inc. and Extreme DA(TM) announced that they have jointly developed an essential statistical design flow for integrated circuit (IC) designs manufactured at process nodes of 65-nanometers (nm) and below. Successful statistical static timing analysis (SSTA) using Altos' Variety(TM) models with the Extreme DA GoldTime(TM) analyzer has been verified by several mutual customers.
SMIC Offers CPF Digital Reference Flow, Joins Power Forward Initiative
Semiconductor Manufacturing International Corporation (SMIC) (NYSE: SMI; SEHK: 0981.HK), the largest semiconductor foundry in China, and Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that SMIC is offering a Common Power Format (CPF)-based 90-nanometer low-power digital reference flow and CPF-compliant libraries. SMIC also announced that it has joined the Power Forward Initiative (PFI).
SMIC, Magma Create Enhanced Reference Flow for 90nm Low-Power Process
Semiconductor Manufacturing International Corporation ("SMIC", NYSE: SMI; HKSE: 981), one of the leading foundries in the world, and Magma(R) Design Automation Inc. (Nasdaq: LAVA), a provider of semiconductor design software, jointly announced the availability of an enhanced low-power IC implementation reference flow for SMIC's 90-nanometer (nm) process featuring Magma's Blast Power(TM), Blast Fusion(R) and Blast Create(TM).
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