Magma Unveils Talus RTL-to-GDSII Reference Flow for MIPS Processor IP
Magma® Design Automation (Nasdaq: LAVA), a provider of chip design software, announced availability of a validated Talus®-based RTL-to-GDSII reference flow for system-on-chip (SoC) designs that incorporate high-performance embedded microprocessor cores from MIPS Technologies, Inc. (NASDAQ: MIPS), including the MIPS32® 1004K[tm], 74K®, 34K® and 24K® families. With this reference flow and the MIPS® IP, mutual customers can achieve repeatable results and speed deployment of advanced SoCs.
TSMC Validates Magma Titan and FineSim for AMS Reference Flow
Magma® Design Automation (Nasdaq: LAVA), a provider of chip design software, announced TSMC has validated the Titan[tm] Mixed-Signal Design Platform and FineSim[tm] SPICE and FineSim Pro circuit simulation products for TSMC’s first Analog/Mixed-Signal (AMS) Reference Flow inclusion, targeting its most advanced 28-nanometer (nm) process technology. The TSMC AMS Reference Flow 1.0 aims to address advanced process effects to accelerate next-generation analog/mixed-signal IC designs. The combination of the AMS Reference Flow and Magma’s Titan Mixed-Signal Design Platform and FineSim circuit simulator provide users with an integrated front-end and back-end analog design solution that accelerates time-to-market by improving designer productivity and enabling analog design reuse.
TSMC Debuts Reference Flow 11.0, Analog Mixed Signal Reference Flow
Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) introduced Reference Flow 11.0 and Analog/Mixed Signal (AMS) Reference Flow 1.0. Both are key collaborative components of TSMC’s recently-announced extension of its Open Innovation Platform[TM]. Reference Flow 11.0, focuses on Electronic System Level (ESL) design, SoC Interconnect Fabric, and two dimensional and three dimensional integrated circuits (2-D/3-D ICs) using through silicon via (TSV) technology. AMS Reference Flow 1.0 offers advanced multi-vendor AMS design flow fully integrated with an innovative TSMC AMS design package to manage the growing complexity of process effects as well as design complexity at 40nm and 28nm process nodes.
SynTest DFT PRO Plus Integrates with Magma Talus RTL-to-GDSII Design Flow
Magma® Design Automation (Nasdaq: LAVA), a provider of chip design software, announced a collaborative effort with MagmaTies Partner SynTest Technologies, Inc., provider of design-for-test (DFT) solutions, to integrate SynTest DFT PRO Plus products into Magma’s Talus® RTL-to-GDSII IC design flow. The integration complements Magma’s scan-based DFT methodology and mutual customers have validated the flow.
Imperas Debuts Embedded Software Flow with Mentor Nucleus RTOS, EDGE
Imperas announced a flow with Mentor Graphics Corporation (Nasdaq: MENT) focused on enabling more productive and higher quality embedded software development with the Mentor Graphics® Nucleus Real-Time Operating System (RTOS) and the Mentor Embedded[TM] software tools. With firmware and application software development taking the majority of the resources for developing embedded, creating new flows for embedded software is increasingly important. The Imperas flow with Mentor Graphics Embedded Software Division (ESD) tools, including the Mentor Nucleus RTOS and EDGE products, makes it easier to use the Open Virtual Platforms (OVP) open source models for the development of embedded systems.
Cadence Expands Support for TSMC 65nm Integrated Signoff Flow
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it increases tool support in TSMC’s 65-nanometer Integrated Signoff Flow by introducing RTL Compiler, EDI System, QRC Extraction and Encounter Timing System for Signal Integrity into it. By following fully validated, scripted and documented procedures within TSMC’s Integrated Signoff Flow, mutual customers can now establish an end-to-end RTL-to-GDSII flow with predictable, shorter time-to-volume for their 65-nanometer designs.
TSMC ISF Features Azuro PowerCentric Clock Tree Synthesis Tool
Azuro, Inc., a leading provider of advanced clock tree synthesis and timing optimization tools for digital chip design, announced the inclusion of its PowerCentric[tm] low power clock tree synthesis tool in the second release of TSMC’s Integrated Sign-off Flow (ISF) in 65nm. The ISF is an automated RTL to GDSII chip implementation flow that tightly integrates TSMC foundry technology files, pre-qualified library, IP, EDA tools, and sign-off margin recommendations into a fully automated scripted production-quality flow that has been proven and refined over hundreds of applications. With this second release of the ISF, TSMC customers are able to tapeout with PowerCentric using either a Cadence or Synopsys based P&R flow and reduce clock power by 25% or more.
TSMC Integrated Sign-off Flow Features Magma Quartz DRC, Quartz LVS
Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, announced that TSMC has selected Quartz[tm] DRC and Quartz LVS for physical verification in TSMC’s Integrated Sign-off Flow (ISF). TSMC provides certified flow comprising proven, best-in-class tools to enable the fastest path to TSMC silicon. The flow is now available for 65-nanometer (nm) designs.
Tensilica Design Flow Supports Synopsys Galaxy Implementation Platform
Tensilica,® Inc. announced that it now provides out-of-the-box automated design flow support for key technologies within Synopsys’ Galaxy[tm] Implementation Platform, including DC Ultra RTL synthesis and IC Compiler place-and-route, for Tensilica’s new Xtensa 8 and Xtensa LX3 dataplane processors (DPUs). This latest design flow provides up to 15 percent improvement in processor speed, area and power, in addition to faster design closure over previous Synopsys-based design flows, thus offering immediate benefits to Tensilica customers.
TSMC Integrated Sign-off Flow Features Calibre Physical Verification
Mentor Graphics Corporation (NASDAQ: MENT) announced that Taiwan Semiconductor Manufacturing Company (TSMC) selected the Calibre® physical verification platform for its Integrated Sign-Off (ISO) Flow, which integrates tools, setup files, and flow management utilities to provide mutual customers with an automated design solution for implementing their chips in TSMC technologies. The new flow is now available for 65nm designs with planned extensions into other process technology nodes.
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