EDA Geek » Design Flow

Design Flow for Heterogeneous 3D Stacked ICs

Ken Cheung — Thu, 26 May 2011 14:18:02 +0000

Atrenta and imec teamed together to develop an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs. 3D stacked ICs feature reduced footprint with shorter and faster interconnects, increased system integration at a lower cost, and higher modularity and reuse. 3D stacked ICs are ideal for mobile and high-performance applications, imagers, stacked DRAM, and solid-state drives.

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HHNEC-Synopsys 130nm Reference Flow 3.0

Ken Cheung — Tue, 03 May 2011 14:56:37 +0000

Synopsys and Shanghai Hua Hong NEC Electronics Company teamed on a 130-nanomter (nm) reference flow. The HHNEC-Synopsys Reference Flow 3.0 features the Synopsys Eclypse Low Power Solution. The reference design flow is available now from HHNEC. With the latest foundry flow, designers can leverage Synopsys’s strength in low power design and HHNEC’s manufacturing expertise.

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Cadence Enhanced Unified Custom Analog Flow

Ken Cheung — Mon, 14 Mar 2011 18:29:44 +0000

Cadence Design Systems has enhanced their Virtuoso-based custom/analog flow. The expanded custom/analog flow helps designers manage design parasitics, a DFM capability integrated within the Virtuoso environment, and the integrated Virtuoso Power System. The new features increase productivity across the entire flow from initial design specification to final GDSII and for process nodes down to 20 nanometers. The custom analog flow includes Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation technologies, Virtuoso Layout Suite, Virtuoso Power System, and Virtuoso DFM.

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Synopsys, TowerJazz Team on Analog Mixed-Signal Power Management

Ken Cheung — Wed, 17 Nov 2010 18:11:06 +0000

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and TowerJazz (NASDAQ: TSEM, TASE: TSEM), the global specialty foundry leader, announced that they have collaborated to qualify Synopsys’ custom design solution with TowerJazz’s 180-nanometer (nm) power management (PM) interoperable process design kit (iPDK) and analog/mixed-signal (AMS) PM reference flow. The qualified solution from Synopsys includes the Galaxy Custom Designer® implementation, HSPICE® circuit simulation, CustomSim[tm] FastSPICE simulation, and StarRC[tm] parasitic extraction tools. The TowerJazz AMS PM Reference Flow with the 180-nm iPDK provides mutual customers with a comprehensive, productive and open custom design solution.

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Synopsys, SMIC Announce SoC Reference Flow for 65nm Process

Ken Cheung — Mon, 15 Nov 2010 17:00:30 +0000

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981), announced that they have delivered a comprehensive solution for system-on-chip (SoC) design for SMIC’s advanced 65-nanometer (nm) process. The solution integrates Synopsys’ broad DesignWare[tm] interface and analog IP portfolio plus other foundation IP with Synopsys’ Galaxy[tm] Implementation Platform, in a tuned reference flow. The companies have also begun work on their 40-nm design solution. Based on collaboration agreements for 65-nm and 40-nm, SMIC has selected Synopsys as the main supplier for design implementation software and IP solutions consisting of digital controllers, PHYs and analog IP.

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Atrenta, TSMC Team on Synthesizable IP for SpyGlass Platform

Ken Cheung — Thu, 21 Oct 2010 16:34:07 +0000

Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, disclosed details of a collaboration with TSMC to enhance the quality of delivered synthesizable IP using Atrenta’s SpyGlass® platform. SpyGlass is Atrenta’s register transfer level (RTL) analysis and optimization product suite that analyzes and optimizes the quality of integrated circuit designs early in the design process, before expensive and time-consuming physical implementation begins.

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Magma Debuts Hierarchical Reference Flow for Low-Power Process

Ken Cheung — Wed, 01 Sep 2010 15:51:11 +0000

Magma® Design Automation (Nasdaq: LAVA), announced the availability of a proven hierarchical RTL-to-GDSII reference flow for the Common Platform[tm] alliance’s 32/28nm low-power process technology. This automated, comprehensive solution provides predictable results and reduces development costs for 2-million-instance and larger systems on chip (SoCs) that are manufactured at this advanced process node.

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Cadence, ARM Optimize System Realization Solution for Processors

Ken Cheung — Wed, 21 Jul 2010 19:25:06 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced a broadening of its existing collaboration with ARM to develop an optimized System Realization solution for ARM processors that will enable an end-to-end flow including a full set of interoperable tools, ARM® processor and physical IP, services and methodology from embedded Linux to GDSII. To accelerate adoption of this solution, Cadence will provide a full complement of tutorials and education materials including two methodology reference books and extend their ecosystem of service, methodology and training providers.

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TSMC Reference Flow 11 Features XtractIM, OrbitIO Planner, OptimizePI

Ken Cheung — Tue, 29 Jun 2010 07:01:18 +0000

Sigrity, Inc., the market leader in signal and power integrity solutions, announced that TSMC has included three Sigrity chip, package and system co-design products – XtractIM, OrbitIO Planner and OptimizePI – in its new TSMC Reference Flow 11.0. Companies that rely on TSMC flow support now can benefit from streamlined IC package assessment, package model extraction, chip/system IO planning, and power delivery system optimization.

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TSMC Reference Flow 11 Features Carbon Model Studio, SoC Designer Plus

Ken Cheung — Mon, 21 Jun 2010 18:45:44 +0000

Carbon Design Systems announced that TSMC added Carbon Model Studio and SoC Designer Plus to TSMC Reference Flow 11.0. The Carbon products used in Reference Flow 11.0 support performance and power analysis at the System (ESL) and register transfer level (RTL), and also provide a platform for pre-silicon software development.

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Magma Unveils Talus RTL-to-GDSII Reference Flow for MIPS Processor IP

Ken Cheung — Thu, 17 Jun 2010 11:01:22 +0000

Magma® Design Automation (Nasdaq: LAVA), a provider of chip design software, announced availability of a validated Talus®-based RTL-to-GDSII reference flow for system-on-chip (SoC) designs that incorporate high-performance embedded microprocessor cores from MIPS Technologies, Inc. (NASDAQ: MIPS), including the MIPS32® 1004K[tm], 74K®, 34K® and 24K® families. With this reference flow and the MIPS® IP, mutual customers can achieve repeatable results and speed deployment of advanced SoCs.

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TSMC Validates Magma Titan and FineSim for AMS Reference Flow

Ken Cheung — Wed, 16 Jun 2010 21:09:46 +0000

Magma® Design Automation (Nasdaq: LAVA), a provider of chip design software, announced TSMC has validated the Titan[tm] Mixed-Signal Design Platform and FineSim[tm] SPICE and FineSim Pro circuit simulation products for TSMC’s first Analog/Mixed-Signal (AMS) Reference Flow inclusion, targeting its most advanced 28-nanometer (nm) process technology. The TSMC AMS Reference Flow 1.0 aims to address advanced process effects to accelerate next-generation analog/mixed-signal IC designs. The combination of the AMS Reference Flow and Magma’s Titan Mixed-Signal Design Platform and FineSim circuit simulator provide users with an integrated front-end and back-end analog design solution that accelerates time-to-market by improving designer productivity and enabling analog design reuse.

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TSMC Debuts Reference Flow 11.0, Analog Mixed Signal Reference Flow

Ken Cheung — Wed, 09 Jun 2010 11:33:07 +0000

Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) introduced Reference Flow 11.0 and Analog/Mixed Signal (AMS) Reference Flow 1.0. Both are key collaborative components of TSMC’s recently-announced extension of its Open Innovation Platform[TM]. Reference Flow 11.0, focuses on Electronic System Level (ESL) design, SoC Interconnect Fabric, and two dimensional and three dimensional integrated circuits (2-D/3-D ICs) using through silicon via (TSV) technology. AMS Reference Flow 1.0 offers advanced multi-vendor AMS design flow fully integrated with an innovative TSMC AMS design package to manage the growing complexity of process effects as well as design complexity at 40nm and 28nm process nodes.

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SynTest DFT PRO Plus Integrates with Magma Talus RTL-to-GDSII Design Flow

Ken Cheung — Tue, 08 Jun 2010 16:42:38 +0000

Magma® Design Automation (Nasdaq: LAVA), a provider of chip design software, announced a collaborative effort with MagmaTies Partner SynTest Technologies, Inc., provider of design-for-test (DFT) solutions, to integrate SynTest DFT PRO Plus products into Magma’s Talus® RTL-to-GDSII IC design flow. The integration complements Magma’s scan-based DFT methodology and mutual customers have validated the flow.

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Imperas Debuts Embedded Software Flow with Mentor Nucleus RTOS, EDGE

Ken Cheung — Tue, 25 May 2010 11:33:25 +0000

Imperas announced a flow with Mentor Graphics Corporation (Nasdaq: MENT) focused on enabling more productive and higher quality embedded software development with the Mentor Graphics® Nucleus Real-Time Operating System (RTOS) and the Mentor Embedded[TM] software tools. With firmware and application software development taking the majority of the resources for developing embedded, creating new flows for embedded software is increasingly important. The Imperas flow with Mentor Graphics Embedded Software Division (ESD) tools, including the Mentor Nucleus RTOS and EDGE products, makes it easier to use the Open Virtual Platforms (OVP) open source models for the development of embedded systems.

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Cadence Expands Support for TSMC 65nm Integrated Signoff Flow

Ken Cheung — Tue, 13 Apr 2010 11:01:59 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it increases tool support in TSMC’s 65-nanometer Integrated Signoff Flow by introducing RTL Compiler, EDI System, QRC Extraction and Encounter Timing System for Signal Integrity into it. By following fully validated, scripted and documented procedures within TSMC’s Integrated Signoff Flow, mutual customers can now establish an end-to-end RTL-to-GDSII flow with predictable, shorter time-to-volume for their 65-nanometer designs.

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TSMC ISF Features Azuro PowerCentric Clock Tree Synthesis Tool

Ken Cheung — Mon, 12 Apr 2010 23:03:51 +0000

Azuro, Inc., a leading provider of advanced clock tree synthesis and timing optimization tools for digital chip design, announced the inclusion of its PowerCentric[tm] low power clock tree synthesis tool in the second release of TSMC’s Integrated Sign-off Flow (ISF) in 65nm. The ISF is an automated RTL to GDSII chip implementation flow that tightly integrates TSMC foundry technology files, pre-qualified library, IP, EDA tools, and sign-off margin recommendations into a fully automated scripted production-quality flow that has been proven and refined over hundreds of applications. With this second release of the ISF, TSMC customers are able to tapeout with PowerCentric using either a Cadence or Synopsys based P&R flow and reduce clock power by 25% or more.

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TSMC Integrated Sign-off Flow Features Magma Quartz DRC, Quartz LVS

Ken Cheung — Tue, 06 Apr 2010 17:28:15 +0000

Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, announced that TSMC has selected Quartz[tm] DRC and Quartz LVS for physical verification in TSMC’s Integrated Sign-off Flow (ISF). TSMC provides certified flow comprising proven, best-in-class tools to enable the fastest path to TSMC silicon. The flow is now available for 65-nanometer (nm) designs.

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Tensilica Design Flow Supports Synopsys Galaxy Implementation Platform

Ken Cheung — Tue, 08 Dec 2009 18:01:11 +0000

Tensilica,® Inc. announced that it now provides out-of-the-box automated design flow support for key technologies within Synopsys’ Galaxy[tm] Implementation Platform, including DC Ultra RTL synthesis and IC Compiler place-and-route, for Tensilica’s new Xtensa 8 and Xtensa LX3 dataplane processors (DPUs). This latest design flow provides up to 15 percent improvement in processor speed, area and power, in addition to faster design closure over previous Synopsys-based design flows, thus offering immediate benefits to Tensilica customers.

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TSMC Integrated Sign-off Flow Features Calibre Physical Verification

Ken Cheung — Thu, 22 Oct 2009 15:31:04 +0000

Mentor Graphics Corporation (NASDAQ: MENT) announced that Taiwan Semiconductor Manufacturing Company (TSMC) selected the Calibre® physical verification platform for its Integrated Sign-Off (ISO) Flow, which integrates tools, setup files, and flow management utilities to provide mutual customers with an automated design solution for implementing their chips in TSMC technologies. The new flow is now available for 65nm designs with planned extensions into other process technology nodes.

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Cadence, ARM Team on Next Generation SoC Design Flow

Ken Cheung — Wed, 21 Oct 2009 11:31:53 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, and ARM, Ltd. [(LSE: ARM); (Nasdaq: ARMH)] announced that the two companies have entered into a strategic collaboration to create a next-generation SoC design flow that will accelerate time to market and lower the cost of SoC integration and verification. Under the terms of the agreement, the Cadence® Chip Planning System and Cadence Incisive® functional verification solutions will be combined with ARM® AMBA® Designer, Performance Exploration tools and Network Interconnect IP.

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Cadence, STARC Team on Next-Generation Analog Mixed-Signal Reference Flow

Ken Cheung — Mon, 19 Oct 2009 16:08:26 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it will collaborate with STARC to develop the Japanese electronic design consortium’s next-generation analog/mixed-signal reference flow. Cadence and STARC will use Cadence® Virtuoso® IC 6.1 technology as the platform for developing the STARCAD-AMS flow. STARC is a consortium made up of 10 electronics companies, six of whom participate in the areas of analog and mixed-signal design.

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TSMC Reference Flow 10.0 Features Mentor Graphics Low Power Solution

Ken Cheung — Mon, 21 Sep 2009 17:11:13 +0000

Mentor Graphics Corporation (NASDAQ:MENT) announced that its low power RTL-to-GDSII tool flow has been included in Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) Reference Flow 10.0. TSMC and Mentor worked together nearly a year to validate and deliver a robust set of tools with proven support for the Unified Power Format (UPF). “In addition to expanding the Mentor reference flow to add both functional verification and implementation technologies, Mentor is addressing new challenges such as low power,” said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.

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STARC Implements Cadence Encounter for Designs Over 20 Million Gates

Ken Cheung — Thu, 09 Jul 2009 16:39:07 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, announced that the Japanese electronic design consortium STARC is implementing a Cadence® flow for semiconductor designs larger than 20 million gates. The new STARCAD-CEL V3.0 methodology for large-scale design was defined by the consortium to describe a comprehensive, RTL-to-GDSII design methodology for quickly designing semiconductor systems of this size. After extensive evaluation, the Cadence Encounter® platform and methodology met all necessary STARC requirements.

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STARC Litho-Aware 45nm DFM Design Flow Features Cadence Encounter

Ken Cheung — Thu, 09 Jul 2009 16:28:23 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, announced the Japanese semiconductor research consortium STARC (Semiconductor Technology Academic Research Center), has integrated the Cadence® Encounter® Digital Implementation System, with its integrated DFM technologies, as its DFM flow targeting 45 nanometer designs and below. The comprehensive DFM suite integrates Cadence Litho Physical Analyzer (LPA), Cadence Litho Electrical Analyzer (LEA), and Cadence CMP Predictor into the designer’s cockpit. Using the Cadence enabled STARCAD-CEL V3.0 Ref Flow, designers gain ready access to process-accurate manufacturing information early in the physical design flow, where engineers can leverage the seamless integration in digital implementation to identify, analyze and correct yield-limiting hotspots for their advanced-node designs. In addition, with Litho Electrical Analyzer, designers can analyze the litho impact on transistor performance and make necessary design trade-offs to meet their design criteria.

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Duolog Socrates Chip Integration Platform Integrates with Arteris NoC

Ken Cheung — Mon, 15 Jun 2009 21:49:06 +0000

Arteris Inc., the leading developer of Network on Chip (NoC) solutions, and Duolog, a provider of SoC integration tools, announced the integration of Duolog design tools with Arteris’ NoC solution to provide designers a more streamlined and efficient way to integrate multiple semiconductor intellectual property (IP) blocks on a single system on chip (SoC) device. The integration leverages Arteris’ NoC solution for enabling high-performance on-chip interconnect and communications, and Duolog’s Socrates[tm] Chip Integration Platform, which is a suite of tools for capturing, viewing and validating various elements of the infrastructure of complex SoCs.

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Agilent Announces TriQuint PDK for TQPED GaSs E/D pHEMT Process

Ken Cheung — Mon, 08 Jun 2009 22:48:51 +0000

Agilent Technologies Inc. (NYSE:A) announced the availability of a powerful foundry-certified process design kit (PDK) to support TriQuint Semiconductor’s popular TQPED GaSs E/D pHEMT process. Providing the most complete MMIC design flow available using Agilent’s Advanced Design System (ADS) platform, the new TQPED PDK completely renovates layout functions, adds many design automation and routing capabilities, and provides a MMIC toolbar personality to help streamline the MMIC design process. The PDK is available now from TriQuint.

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3L Becomes Member of Texas Instruments Developer Network

Ken Cheung — Wed, 20 May 2009 16:35:57 +0000

3L, the Multiprocessor Design Company, announced that it has joined the Texas Instruments Incorporated (TI) Developer Network as a provider of multiprocessor design solutions. The announcement strengthens 3L’s multiprocessor design flow targeting TI digital signal processors (DSPs) and offers tighter integration between 3L’s Diamond multiprocessor tool suite and the TI portfolio of DSPs as well as Code Composer Studio (CCStudio) integrated development environment (IDE).

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Forte Announces Electronic System Level Design Flow Seminars

Ken Cheung — Fri, 01 May 2009 16:56:44 +0000

Forte Design Systems, a leading provider of SystemC-based High Level Synthesis software, will kick off a series of training seminars in May for semiconductor companies to better understand how to implement an electronic system level (ESL) design flow. The two-part series, scheduled to start May 11 in Korea, with additional dates in Japan, the United States and Europe throughout 2009, is designed for hardware engineers and their managers.

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Encounter Conformal Constraint Designer Qualifies for STARCAD-CEL Flow

Ken Cheung — Fri, 16 Jan 2009 00:37:53 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global design innovation, announced that the Semiconductor Technology Academic Research Center (STARC) in Japan has qualified the Cadence® Encounter® Conformal® Constraint Designer for use in the STARCAD-CEL design flow for advanced semiconductor design. The qualification demonstrates that Encounter Conformal Constraint Designer has delivered production-quality results and provides a robust solution for the various requirements of multiple STARC member companies.

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