'Design Flow' Category Archive

Cadence Debuts RTL to GDSII Reference Flows for ARM Cortex-A9

Posted by EDA Geek News Staff in Design Flow on Tuesday, April 29, 2008

Cadence Design Systems, Inc. (NASDAQ: CDNS) announced the immediate availability of multiple, silicon-ready RTL to GDSII implementation flows based on the Cadence® Encounter® digital IC design platform, for the ARM® Cortex(tm)-A9 processor. The flows are available for three configurations of the ARM Cortex-A9 processor: single core, dual Cortex-A9 MPCore(tm) multicore processor and quad Cortex-A9 MPCore(tm) multicore processor. Proven to enable ARM Cortex-A9 processor performance of up to 800MHz (production-margined at worst case PVT conditions), these reference methodologies offer time-to-market savings for customers designing for high performance within tight power constraints for next-generation devices such as smart phones, mobile internet devices, consumer electronics, automotive infotainment, networking and other embedded and enterprise devices.

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STARC STARCAD-CEL 2.0 Design Flow Features Atrenta Tools

Posted by EDA Geek News Staff in Design Flow on Wednesday, April 23, 2008

Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, announced the integration of its SpyGlass®, SpyGlass-Constraints, SpyGlass-DFT, SpyGlass-Power, and 1Team®-Implement products into the latest production flow from the Semiconductor Technology Academic Research Center (STARC). Called STARCAD-CEL Version 2.0, the new production flow supports RTL analysis as well as chip implementation, offering a comprehensive solution for early constraints analysis and management, design-for-test (DFT), low power design, and design feasibility analysis. The Atrenta products were proven effective in the STARCAD-CEL reference flows.

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CoWare, Sonics Announce ESL 2.0 Upgrade of Integrated Design Flow

Posted by EDA Geek News Staff in Design Flow on Wednesday, March 26, 2008

CoWare® Inc., the leading supplier of platform-driven electronic system-level (ESL) design software and services, and Sonics Inc., a premier supplier of system-on-chip (SoC) SMART Interconnect(tm) solutions, announced availability of the ESL 2.0 upgrade of their joint flow. The integration provides designers a single flow with advanced debugging and analysis capabilities for platform architecture design and platform verification using Sonics SMART interconnection solutions.

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STARC STARCAD-CEL 2.0 Flow Features FishTail Focus, Confirm Tools

Posted by EDA Geek News Staff in Design Flow on Wednesday, March 19, 2008

FishTail Design Automation, Inc., the golden timing constraints company, announced that Japan's Semiconductor Technology Academic Research Center (STARC) has released a new production flow for chip implementation using FishTail's technology for timing exception generation and verification. The STARCAD-CEL Version 2.0 flow includes the use of FishTail products Focus(tm) and Confirm(tm) to generate and verify false and multi-cycle paths on complex SoC designs.

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IMEC Introduces Variability Aware Modeling Flow for Sub-45nm

Posted by EDA Geek News Staff in Design Flow on Tuesday, March 11, 2008

IMEC reports a variability-aware modeling (VAM) flow that analyzes process variability of sub-45nm technologies which enables designers to optimize their system design for timing, energy and yield versus expected application load. The flow assesses the impact of process variations and degradation effects of sub-45nm technologies on the system performance by giving valuable information to the designer. IMEC's VAM flow can hook into commercial design for manufacturing (DFM) tools and has been validated on industrial process technology data and IP cores.

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Tela Innovations Shares Vision for Design Solution at 45nm and Beyond

Posted by EDA Geek News Staff in Design Flow on Wednesday, February 27, 2008

Tela Innovations, an early-stage technology company focused on addressing the challenges of scaling semiconductor manufacturing to 45nm and beyond, unveiled its business strategy and technology vision for using on-grid, straight-line, one-dimensional layout structures to provide a more efficient and reliable way to design and manufacture next generation chips. Details of the solution were disclosed at the SPIE Advanced Lithography Conference in joint presentations from Tela and ASML/Brion and Applied Materials.

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