Category Archives: Design Flow

Design Flow for Heterogeneous 3D Stacked ICs

Atrenta and imec teamed together to develop an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs. 3D stacked ICs feature reduced footprint with shorter and faster interconnects, increased system integration at a lower cost, and higher modularity and reuse. 3D stacked ICs are ideal for mobile and high-performance applications, imagers, stacked DRAM, and solid-state drives.

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HHNEC-Synopsys 130nm Reference Flow 3.0

Synopsys and Shanghai Hua Hong NEC Electronics Company teamed on a 130-nanomter (nm) reference flow. The HHNEC-Synopsys Reference Flow 3.0 features the Synopsys Eclypse Low Power Solution. The reference design flow is available now from HHNEC. With the latest foundry flow, designers can leverage Synopsys’s strength in low power design and HHNEC’s manufacturing expertise.

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Cadence Enhanced Unified Custom Analog Flow

Cadence Design Systems has enhanced their Virtuoso-based custom/analog flow. The expanded custom/analog flow helps designers manage design parasitics, a DFM capability integrated within the Virtuoso environment, and the integrated Virtuoso Power System. The new features increase productivity across the entire flow from initial design specification to final GDSII and for process nodes down to 20 nanometers. The custom analog flow includes Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation technologies, Virtuoso Layout Suite, Virtuoso Power System, and Virtuoso DFM.

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Synopsys, TowerJazz Team on Analog Mixed-Signal Power Management

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and TowerJazz (NASDAQ: TSEM, TASE: TSEM), the global specialty foundry leader, announced that they have collaborated to qualify Synopsys’ custom design solution with TowerJazz’s 180-nanometer (nm) power management (PM) interoperable process design kit (iPDK) and analog/mixed-signal (AMS) PM reference flow. The qualified solution from Synopsys includes the Galaxy Custom Designer® implementation, HSPICE® circuit simulation, CustomSim[tm] FastSPICE simulation, and StarRC[tm] parasitic extraction tools. The TowerJazz AMS PM Reference Flow with the 180-nm iPDK provides mutual customers with a comprehensive, productive and open custom design solution.

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Synopsys, SMIC Announce SoC Reference Flow for 65nm Process

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981), announced that they have delivered a comprehensive solution for system-on-chip (SoC) design for SMIC’s advanced 65-nanometer (nm) process. The solution integrates Synopsys’ broad DesignWare[tm] interface and analog IP portfolio plus other foundation IP with Synopsys’ Galaxy[tm] Implementation Platform, in a tuned reference flow. The companies have also begun work on their 40-nm design solution. Based on collaboration agreements for 65-nm and 40-nm, SMIC has selected Synopsys as the main supplier for design implementation software and IP solutions consisting of digital controllers, PHYs and analog IP.

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Atrenta, TSMC Team on Synthesizable IP for SpyGlass Platform

Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, disclosed details of a collaboration with TSMC to enhance the quality of delivered synthesizable IP using Atrenta’s SpyGlass® platform. SpyGlass is Atrenta’s register transfer level (RTL) analysis and optimization product suite that analyzes and optimizes the quality of integrated circuit designs early in the design process, before expensive and time-consuming physical implementation begins.

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Magma Debuts Hierarchical Reference Flow for Low-Power Process

Magma® Design Automation (Nasdaq: LAVA), announced the availability of a proven hierarchical RTL-to-GDSII reference flow for the Common Platform[tm] alliance’s 32/28nm low-power process technology. This automated, comprehensive solution provides predictable results and reduces development costs for 2-million-instance and larger systems on chip (SoCs) that are manufactured at this advanced process node.

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Cadence, ARM Optimize System Realization Solution for Processors

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced a broadening of its existing collaboration with ARM to develop an optimized System Realization solution for ARM processors that will enable an end-to-end flow including a full set of interoperable tools, ARM® processor and physical IP, services and methodology from embedded Linux to GDSII. To accelerate adoption of this solution, Cadence will provide a full complement of tutorials and education materials including two methodology reference books and extend their ecosystem of service, methodology and training providers.

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TSMC Reference Flow 11 Features XtractIM, OrbitIO Planner, OptimizePI

Sigrity, Inc., the market leader in signal and power integrity solutions, announced that TSMC has included three Sigrity chip, package and system co-design products – XtractIM, OrbitIO Planner and OptimizePI – in its new TSMC Reference Flow 11.0. Companies that rely on TSMC flow support now can benefit from streamlined IC package assessment, package model extraction, chip/system IO planning, and power delivery system optimization.

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TSMC Reference Flow 11 Features Carbon Model Studio, SoC Designer Plus

Carbon Design Systems announced that TSMC added Carbon Model Studio and SoC Designer Plus to TSMC Reference Flow 11.0. The Carbon products used in Reference Flow 11.0 support performance and power analysis at the System (ESL) and register transfer level (RTL), and also provide a platform for pre-silicon software development.

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