Cadence Donates Wreal Model to Accellera Standards Group
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it has contributed to the Accellera standards organization new technology that can help engineers conduct faster and more thorough functional verification on complex mixed-signal SoCs. Cadence® donated a set of extensions to the wreal feature of the Verilog-AMS real numbered modeling capability. These Cadence extensions are designed to improve accuracy and offer better plug-and-play with analog models. Wreal enables engineers to conduct functional verification on these SoCs at digital speed. Faster and deeper verification can translate to fewer re-spins and faster time to market.
STMicroelectronics Offers Free Version of Cadence OrCAD PSpice
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that STMicroelectronics, a global leader in integrated circuits for communications, consumer, computer, automotive and industrial applications, has selected Cadence® OrCAD® PSpice® technology to provide simulation capabilities to its customers to evaluate the company’s analog and power IC’s.
Konica Minolta Designs LSI with EVE ZeBu Emulation Platform
EVE, the leader in hardware/software co-verification, announced Konica Minolta Technology Center, Inc., of Tokyo, Japan, has selected its ZeBu (for Zero Bugs) hardware-assisted verification platform for the design of its high-speed, high-performance large-scale integrated circuits (LSIs) used in image processing.
Imperas Creates Models for MIPS32 M14K, M14Kc Processor Cores
Imperas released models of the new MIPS32® M14K[tm] and M14Kc[tm] processor cores from MIPS Technologies, Inc., including example virtual platforms utilizing these cores and support for the cores in Imperas’ advanced software development tools. The M14K family of processors is the first to support the new microMIPS code compression instruction set architecture (ISA) from MIPS Technologies, which is fully supported in the Imperas models. MIPS Technologies has verified the functionality of these models under the MIPS-Verified[tm] program.
OMG, Wireless Innovation Forum Offer Membership Discounts
Leaders of computer industry standards organization OMG[tm] and reconfigurable radio technologies industry association The Wireless Innovation Forum met recently at a joint meeting of the Wireless Innovation Forum and JTRS JPEO, to discuss ways they can better serve the members of both organizations. Key outputs resulting from this meeting include a plan to develop a whitepaper highlighting the process followed and success achieved in the joint development of the “PIM and PSM for Smart Antenna” specification, and discounts on first-year membership for members of each organization to join the other to simplify and support collaborative development in the future.
Rohde & Schwarz Adopts Cadence Virtuoso Accelerated Parallel Simulator
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that Rohde & Schwarz, a market leader in complex RF test and measurement products, improved the quality and functionality of its complex RF integrated circuits (RFICs) through an increased simulation depth using Cadence® Virtuoso® Accelerated Parallel Simulator (APS).
Carbon Design Systems Unveils Databahn DDR SDRAM Controller IP Models
Denali Software, Inc., a leading provider of intellectual property (IP) and electronic design automation (EDA) software, and Carbon Design Systems announced a collaboration to provide designers with cycle-accurate models of Denali’s configurable Databahn[TM] DDR SDRAM controller IP for virtual platforms. Databahn IP models are available today for use with leading system simulation environments (including Carbon SoC Designer, CoWare Platform Architect, and OSCI SystemC) to perform architectural analysis, validate system performance, and perform hardware/software integration prior to silicon.
Open Virtual Platforms Rolls Out Virage Logic ARC Processors Models
The Open Virtual Platforms (OVP) initiative has announced the release of models of Virage Logic’s ARC processor cores. Models of the Virage Logic ARC® 600 and ARC® 700 families of processor cores have been released, including the ARC® 605. Additionally, Virage Logic and Imperas have cooperated on the verification of the functionality of the models. Virage Logic’s ARC line of processor cores, the world’s second most widely used processor architecture, are commonly used in audio and video subsystems, and in flash controllers, among other applications.
OSCI Releases SystemC Analog Mixed Signal Extensions Language Standard
The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to supporting and advancing SystemC as an industry-standard language for electronic system-level (ESL) design, released the SystemC Analog/Mixed-signal (AMS) extensions language standard, AMS 1.0. The AMS 1.0 standard is the first modeling language targeting system-level design and verification to describe analog/mixed-signal behavior as natural extension to existing SystemC-based design methodologies.
dSPACE, Elektrobit Team on AUTOSAR Tools for Electronic Control Units
dSPACE and EB (Elektrobit), a leading developer of cutting-edge embedded technology solutions for automotive and wireless industries, announced further harmonization of their AUTOSAR tools. This cooperation offers developers of automotive electronic control unit (ECU) software a coordinated tool chain. Using the integrated AUTOSAR modeling and simulation environment SystemDesk, the TargetLink production ready code generator, and the EB tresos Studio configuration tool, developers can efficiently use a model-based approach to designing software, culminating in production-ready AUTOSAR ECU software.
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