SPEculative and Exploratory Design in Systems Engineering Project
The four-year SPEEDS (SPEculative and Exploratory Design in Systems Engineering) project, funded under the European Union’s 6th Framework Programme, has come to a highly successful conclusion. The SPEEDS project has resulted in the definition of a novel end-to-end design methodology, process and tool environment for model-based safety-critical embedded systems that significantly improves design quality while reducing both design cycle times and costs.
Cadence, Fujitsu Team on Chip Package Board Co-Design Solution
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced that, with the assistance of Fujitsu Semiconductor Limited and Fujitsu VLSI Limited (hereafter collectively called Fujitsu), Cadence has developed a standardized die model that provides ASIC and microcontroller (MCU) designers with a comprehensive chip-package-board co-design solution.
Synopsys, IEEE-ISTO Form Interconnect Modeling Technical Advisory Board
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced the open source availability of its widely used Interconnect Technology Format (ITF) for parasitic modeling and the formation of a technical advisory board (TAB) under the auspices of IEEE Industry Standards and Technology Organization (IEEE-ISTO). The purpose of the Interconnect Modeling TAB (IMTAB) is to facilitate the evolution of ITF and promote an interoperable interconnect modeling format to address the industry’s advancing process technology and design needs. IMTAB founding members include representatives from industry-leading semiconductor companies, EDA companies and silicon foundries including Altera Corporation, AMD, Apache Design Solutions, GLOBALFOUNDRIES, LSI Corporation, Magma Design Automation, NVIDIA, Qualcomm, STMicroelectronics and Synopsys. Following the same model as the industry-standard Liberty[TM] library modeling format, ITF access is granted under an open source license through Synopsys’ Technology Access Program (TAP-in(SM)) and is available free of charge to anyone.
VectorCAST/C++ Features Extended Support for Renesas HEW Environment
Vector Software, the leading provider of software test tools for embedded systems, announced extended support for the Renesas High-Performance Embedded Workshop (HEW) development environment. This newest integration enables users to unit test their code and measure code coverage automatically on M16C/R8C and SuperH (SH) simulators.
Cadence Donates Wreal Model to Accellera Standards Group
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it has contributed to the Accellera standards organization new technology that can help engineers conduct faster and more thorough functional verification on complex mixed-signal SoCs. Cadence® donated a set of extensions to the wreal feature of the Verilog-AMS real numbered modeling capability. These Cadence extensions are designed to improve accuracy and offer better plug-and-play with analog models. Wreal enables engineers to conduct functional verification on these SoCs at digital speed. Faster and deeper verification can translate to fewer re-spins and faster time to market.
STMicroelectronics Offers Free Version of Cadence OrCAD PSpice
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that STMicroelectronics, a global leader in integrated circuits for communications, consumer, computer, automotive and industrial applications, has selected Cadence® OrCAD® PSpice® technology to provide simulation capabilities to its customers to evaluate the company’s analog and power IC’s.
Konica Minolta Designs LSI with EVE ZeBu Emulation Platform
EVE, the leader in hardware/software co-verification, announced Konica Minolta Technology Center, Inc., of Tokyo, Japan, has selected its ZeBu (for Zero Bugs) hardware-assisted verification platform for the design of its high-speed, high-performance large-scale integrated circuits (LSIs) used in image processing.
Imperas Creates Models for MIPS32 M14K, M14Kc Processor Cores
Imperas released models of the new MIPS32® M14K[tm] and M14Kc[tm] processor cores from MIPS Technologies, Inc., including example virtual platforms utilizing these cores and support for the cores in Imperas’ advanced software development tools. The M14K family of processors is the first to support the new microMIPS code compression instruction set architecture (ISA) from MIPS Technologies, which is fully supported in the Imperas models. MIPS Technologies has verified the functionality of these models under the MIPS-Verified[tm] program.
OMG, Wireless Innovation Forum Offer Membership Discounts
Leaders of computer industry standards organization OMG[tm] and reconfigurable radio technologies industry association The Wireless Innovation Forum met recently at a joint meeting of the Wireless Innovation Forum and JTRS JPEO, to discuss ways they can better serve the members of both organizations. Key outputs resulting from this meeting include a plan to develop a whitepaper highlighting the process followed and success achieved in the joint development of the “PIM and PSM for Smart Antenna” specification, and discounts on first-year membership for members of each organization to join the other to simplify and support collaborative development in the future.
Rohde & Schwarz Adopts Cadence Virtuoso Accelerated Parallel Simulator
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that Rohde & Schwarz, a market leader in complex RF test and measurement products, improved the quality and functionality of its complex RF integrated circuits (RFICs) through an increased simulation depth using Cadence® Virtuoso® Accelerated Parallel Simulator (APS).
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