EDA Geek » Models, Simulations

UMC Certifies Synopsys StarRC Parasitic Extraction Solution for 28nm Process

Ken Cheung — Wed, 04 Apr 2012 15:30:28 +0000

UMC has certified Synopsys’ StarRC parasitic extraction solution for their latest 28-nanometer (nm) process technologies. UMC’s validation of StarRC extends the benefits of Synopsys’ state-of-the-art process modeling and extraction technology to UMC’s 28-nanometer customers. This enables engineers to deliver high-performance 28-nanometer devices to market with increased confidence.

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Synopsys and Applied Materials Develop Technology Computer-Aided Design Models

Ken Cheung — Thu, 15 Mar 2012 17:21:16 +0000

Synopsys team with Applied Materials to create technology computer-aided design (TCAD) models for next-generation semiconductor devices. The models derived from this TCAD collaboration will enable engineers to speed up process development for 14-nanometer (nm) and 11-nm logic and new memory chip technologies. This will reduce cost and speed time-to-market.

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Fujitsu Laboratories Speeds ARM Simulation by Factor of 100

Ken Cheung — Tue, 13 Mar 2012 17:09:23 +0000

Fujitsu Laboratories Limited has developed the world’s fastest simulation technology for systems using the ARM computing core, which is widely used in mobile phones and other electronic devices. Fujitsu’s simulation technology is able to faithfully reproduce hardware operations with cycle-for-cycle real-time accuracy. The technology will help reduce the development cycle for systems and devices using ARM cores and encourage the development of a greater diversity of ARM-based systems.

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AWR Publishes White Paper on Visual System Simulator Co-simulating with NI LabVIEW

Ken Cheung — Wed, 29 Feb 2012 18:14:12 +0000

AWR has published a white paper. The new article is titled, AWR’s Visual System Simulator Co-simulates with NI’s LabVIEW for Enhanced Signal Processing Capabilities. The technical paper highlights how AWR’s Visual System Simulator (VSS) software and National Instruments’ (NI) LabVIEW graphical programming environment co-simulate and enable designers to analyze, optimize, and verify complex RF circuits, subsystems and digital signal processing within a unified framework.

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D2S TrueMask DS Mask Wafer Double Simulation Accelerated Workstation

Ken Cheung — Wed, 21 Sep 2011 14:24:50 +0000

D2S launched the TrueMask DS mask-wafer double simulation accelerated workstation. It can help mask shops and wafer fabs with qualifying and optimizing 20nm node and below designs. TrueMask is ideal for R&D exploration, bit-cell design, hot-spot analysis and mask-defect categorization that comprehends overlapping eBeam shots and dose modulation. D2S TrueMask DS is available now.

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Synopsys Expands Verification IP Tools by Acquiring nSys Design Systems

Ken Cheung — Fri, 02 Sep 2011 15:52:07 +0000

Synopsys has acquired nSys Design Systems Private Limited. The deal is structured as an acquisition of substantially all the assets and employees of nSys. Other details of the acquisition have not been disclosed. nSys is an independent provider of verification IP (VIP).

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Mentor Graphics Catapult C Supports Transaction Level Models Synthesis

Ken Cheung — Wed, 01 Jun 2011 14:01:55 +0000

According to Mentor Graphics, 87% of respondents in a recent survey indicated it was either mandatory or highly desirable to have high-level synthesis tools integrated with ESL flows. With that in mind, Mentor has enhanced their Catapult C high-level synthesis tool to support the synthesis of transaction level models (TLMs). TLM synthesis results in a TLM 2.0-based solution for virtual prototyping and hardware implementation, and enables the creation of synthesis-ready virtual platforms.

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PrismTech Gains Model-Based Engineering, Acquires Zeligsoft Tools Unit

Ken Cheung — Wed, 27 Oct 2010 14:38:08 +0000

PrismTech[tm], a global leader in standards-based, performance-critical middleware, announced that it has acquired the tools business of Zeligsoft, a leading vendor of model-based development tools for embedded software systems. The acquisition follows on from a successful partnering agreement signed in July 2009 that created Spectra CX, which is now the most widely used SCA-compliant development tool by SDR developers. This immediate success quickly led to acquisition discussions that resulted in this announcement.

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Synopsys HSPICE Precision Parallel Technology Speeds Up Simulation

Ken Cheung — Mon, 20 Sep 2010 17:44:24 +0000

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, unveiled new HSPICE® Precision Parallel (HPP) multi-threading technology that delivers up to 7X simulation speed-up for complex analog and mixed-signal designs. In addition to the new HPP technology, the HSPICE 2010 solution includes enhanced convergence algorithms, advanced analog analysis features and foundry-qualified support for process design kits (PDKs) that extend HSPICE gold-standard accuracy to the verification of complex circuits such as phase-locked loops, SERDES, data converters, high-precision custom digital and power management. With HSPICE 2010, design teams can accelerate verification of their analog circuits across process variation corners and reduce the risk of silicon respins.

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OCP-IP, CircuitSutra, Imperas Announce Virtual Platform Demo

Ken Cheung — Tue, 24 Aug 2010 11:09:32 +0000

Open Core Protocol International Partnership (OCP-IP), the organization delivering a common standard for intellectual property core interfaces that facilitate “plug and play” SoC design, and CircuitSutra, experts in SystemC modeling and embedded software development, along with Imperas, the company providing the infrastructure for the future of software virtual platforms and enabling the next generation of embedded software development, announced the availability of a Virtual Platform Demo created utilizing OCP-IP’s advanced Modeling Kit. This example platform acts as a guide to OCP-IP members enabling them to quick-start their ESL activities using the OCP-IP TLM Modeling Kit; which is fully compatible with OSCI’s TLM 2.0.1. Both the kit and Virtual Platform examples are free to both OCP-IP members and non-members.

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SPEculative and Exploratory Design in Systems Engineering Project

Ken Cheung — Wed, 28 Jul 2010 11:06:00 +0000

The four-year SPEEDS (SPEculative and Exploratory Design in Systems Engineering) project, funded under the European Union’s 6th Framework Programme, has come to a highly successful conclusion. The SPEEDS project has resulted in the definition of a novel end-to-end design methodology, process and tool environment for model-based safety-critical embedded systems that significantly improves design quality while reducing both design cycle times and costs.

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Cadence, Fujitsu Team on Chip Package Board Co-Design Solution

Ken Cheung — Wed, 21 Jul 2010 11:07:44 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced that, with the assistance of Fujitsu Semiconductor Limited and Fujitsu VLSI Limited (hereafter collectively called Fujitsu), Cadence has developed a standardized die model that provides ASIC and microcontroller (MCU) designers with a comprehensive chip-package-board co-design solution.

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Synopsys, IEEE-ISTO Form Interconnect Modeling Technical Advisory Board

Ken Cheung — Wed, 09 Jun 2010 11:01:06 +0000

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced the open source availability of its widely used Interconnect Technology Format (ITF) for parasitic modeling and the formation of a technical advisory board (TAB) under the auspices of IEEE Industry Standards and Technology Organization (IEEE-ISTO). The purpose of the Interconnect Modeling TAB (IMTAB) is to facilitate the evolution of ITF and promote an interoperable interconnect modeling format to address the industry’s advancing process technology and design needs. IMTAB founding members include representatives from industry-leading semiconductor companies, EDA companies and silicon foundries including Altera Corporation, AMD, Apache Design Solutions, GLOBALFOUNDRIES, LSI Corporation, Magma Design Automation, NVIDIA, Qualcomm, STMicroelectronics and Synopsys. Following the same model as the industry-standard Liberty[TM] library modeling format, ITF access is granted under an open source license through Synopsys’ Technology Access Program (TAP-in(SM)) and is available free of charge to anyone.

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VectorCAST/C++ Features Extended Support for Renesas HEW Environment

Ken Cheung — Tue, 04 May 2010 22:20:59 +0000

Vector Software, the leading provider of software test tools for embedded systems, announced extended support for the Renesas High-Performance Embedded Workshop (HEW) development environment. This newest integration enables users to unit test their code and measure code coverage automatically on M16C/R8C and SuperH (SH) simulators.

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Cadence Donates Wreal Model to Accellera Standards Group

Ken Cheung — Thu, 22 Apr 2010 15:37:08 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it has contributed to the Accellera standards organization new technology that can help engineers conduct faster and more thorough functional verification on complex mixed-signal SoCs. Cadence® donated a set of extensions to the wreal feature of the Verilog-AMS real numbered modeling capability. These Cadence extensions are designed to improve accuracy and offer better plug-and-play with analog models. Wreal enables engineers to conduct functional verification on these SoCs at digital speed. Faster and deeper verification can translate to fewer re-spins and faster time to market.

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STMicroelectronics Offers Free Version of Cadence OrCAD PSpice

Ken Cheung — Thu, 08 Apr 2010 15:33:03 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that STMicroelectronics, a global leader in integrated circuits for communications, consumer, computer, automotive and industrial applications, has selected Cadence® OrCAD® PSpice® technology to provide simulation capabilities to its customers to evaluate the company’s analog and power IC’s.

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Konica Minolta Designs LSI with EVE ZeBu Emulation Platform

Ken Cheung — Fri, 02 Apr 2010 11:31:13 +0000

EVE, the leader in hardware/software co-verification, announced Konica Minolta Technology Center, Inc., of Tokyo, Japan, has selected its ZeBu (for Zero Bugs) hardware-assisted verification platform for the design of its high-speed, high-performance large-scale integrated circuits (LSIs) used in image processing.

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Imperas Creates Models for MIPS32 M14K, M14Kc Processor Cores

Ken Cheung — Thu, 01 Apr 2010 11:04:39 +0000

Imperas released models of the new MIPS32® M14K[tm] and M14Kc[tm] processor cores from MIPS Technologies, Inc., including example virtual platforms utilizing these cores and support for the cores in Imperas’ advanced software development tools. The M14K family of processors is the first to support the new microMIPS code compression instruction set architecture (ISA) from MIPS Technologies, which is fully supported in the Imperas models. MIPS Technologies has verified the functionality of these models under the MIPS-Verified[tm] program.

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OMG, Wireless Innovation Forum Offer Membership Discounts

Ken Cheung — Wed, 31 Mar 2010 17:53:26 +0000

Leaders of computer industry standards organization OMG[tm] and reconfigurable radio technologies industry association The Wireless Innovation Forum met recently at a joint meeting of the Wireless Innovation Forum and JTRS JPEO, to discuss ways they can better serve the members of both organizations. Key outputs resulting from this meeting include a plan to develop a whitepaper highlighting the process followed and success achieved in the joint development of the “PIM and PSM for Smart Antenna” specification, and discounts on first-year membership for members of each organization to join the other to simplify and support collaborative development in the future.

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Rohde & Schwarz Adopts Cadence Virtuoso Accelerated Parallel Simulator

Ken Cheung — Wed, 31 Mar 2010 11:03:55 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that Rohde & Schwarz, a market leader in complex RF test and measurement products, improved the quality and functionality of its complex RF integrated circuits (RFICs) through an increased simulation depth using Cadence® Virtuoso® Accelerated Parallel Simulator (APS).

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Carbon Design Systems Unveils Databahn DDR SDRAM Controller IP Models

Ken Cheung — Fri, 26 Mar 2010 11:31:51 +0000

Denali Software, Inc., a leading provider of intellectual property (IP) and electronic design automation (EDA) software, and Carbon Design Systems announced a collaboration to provide designers with cycle-accurate models of Denali’s configurable Databahn[TM] DDR SDRAM controller IP for virtual platforms. Databahn IP models are available today for use with leading system simulation environments (including Carbon SoC Designer, CoWare Platform Architect, and OSCI SystemC) to perform architectural analysis, validate system performance, and perform hardware/software integration prior to silicon.

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Open Virtual Platforms Rolls Out Virage Logic ARC Processors Models

Ken Cheung — Tue, 23 Mar 2010 18:55:10 +0000

The Open Virtual Platforms (OVP) initiative has announced the release of models of Virage Logic’s ARC processor cores. Models of the Virage Logic ARC® 600 and ARC® 700 families of processor cores have been released, including the ARC® 605. Additionally, Virage Logic and Imperas have cooperated on the verification of the functionality of the models. Virage Logic’s ARC line of processor cores, the world’s second most widely used processor architecture, are commonly used in audio and video subsystems, and in flash controllers, among other applications.

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OSCI Releases SystemC Analog Mixed Signal Extensions Language Standard

Ken Cheung — Mon, 08 Mar 2010 19:12:19 +0000

The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to supporting and advancing SystemC as an industry-standard language for electronic system-level (ESL) design, released the SystemC Analog/Mixed-signal (AMS) extensions language standard, AMS 1.0. The AMS 1.0 standard is the first modeling language targeting system-level design and verification to describe analog/mixed-signal behavior as natural extension to existing SystemC-based design methodologies.

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dSPACE, Elektrobit Team on AUTOSAR Tools for Electronic Control Units

Ken Cheung — Thu, 04 Mar 2010 12:06:19 +0000

dSPACE and EB (Elektrobit), a leading developer of cutting-edge embedded technology solutions for automotive and wireless industries, announced further harmonization of their AUTOSAR tools. This cooperation offers developers of automotive electronic control unit (ECU) software a coordinated tool chain. Using the integrated AUTOSAR modeling and simulation environment SystemDesk, the TargetLink production ready code generator, and the EB tresos Studio configuration tool, developers can efficiently use a model-based approach to designing software, culminating in production-ready AUTOSAR ECU software.

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SystemC Configuration, Control & Inspection Standardization Review

Ken Cheung — Mon, 22 Feb 2010 16:34:48 +0000

The Open SystemC Initiative (OSCI), an independent, non-profit organization dedicated to supporting and advancing SystemC[tm] as an industry-standard language for electronic system-level (ESL) design, announced that requirements for the configuration portion of the SystemC Configuration, Control & Inspection (CCI) standardization effort are now available for public review. They are currently available for download under open-source license.

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MagicDraw UML Modeler to Integrate with CoFluent Studio

Ken Cheung — Wed, 17 Feb 2010 12:38:22 +0000

CoFluent Design, a leading Electronic System Level (ESL) company that provides system-level modeling and simulation to accelerate innovation in embedded devices, and No Magic, Inc., the leading global provider of integrated modeling software and services, announced that they have initiated a partnership agreement to integrate the MagicDraw UML (Unified Modeling Language) modeler with the CoFluent Studio embedded system modeling and SystemC-based simulation environment.

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EVE Sponsors Workshop on Architectural Research Prototyping

Ken Cheung — Tue, 16 Feb 2010 12:04:59 +0000

EVE, the leader in hardware/software co-verification and developer of ZeBu-Server, a scalable and affordable emulation system, announced that it will sponsor the 5th Annual Workshop on Architectural Research Prototyping (WARP) to be held June 19 in Saint-Malo, France. It will be collocated with the ACM IEEE International Symposium Computer Architecture (ISCA).

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Wind River to Sell, Support Virtutech Simics Development Platform

Ken Cheung — Fri, 05 Feb 2010 17:01:14 +0000

Wind River, a wholly owned subsidiary of Intel Corporation, announced it will add the Virtutech product line to its embedded software product portfolio after the completion of Intel Corporation’s acquisition of Virtutech signed earlier this week. Virtutech, founded in 1998, is based in San Jose, Calif. and operates a development center in Stockholm, Sweden.

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Synopsys Gains Virtual Prototyping Solutions by Acquiring VaST Systems

Ken Cheung — Wed, 03 Feb 2010 16:42:26 +0000

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced it has acquired VaST Systems Technology Corporation to extend its virtual prototyping solutions into the automotive and consumer application space. The acquisition adds a comprehensive set of processor sub-system models frequently found in automotive and consumer applications to Synopsys’ virtual prototyping portfolio. Processor sub-system models allow developers to accelerate the virtualization of electronic systems and to start software development nine to 12 months prior to the availability of silicon.

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Artisan Software Tools and Aonix Merge to Form Atego

Ken Cheung — Wed, 20 Jan 2010 16:33:38 +0000

Artisan® Software Tools and Aonix® have merged to create a new, stronger independent force in the mission- and safety-critical systems and software development tools market. The merged company is named Atego and headquartered in San Diego CA, USA. Artisan Software Tools is the world’s largest independent supplier of industrial-grade, collaborative modeling tools for complex, mission and safety-critical systems and software and Aonix is a leading supplier of critical systems development tools, virtual machines and services for real-time/embedded Java and Ada solutions.

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