D2S TrueMask DS Mask Wafer Double Simulation Accelerated Workstation
D2S launched the TrueMask DS mask-wafer double simulation accelerated workstation. It can help mask shops and wafer fabs with qualifying and optimizing 20nm node and below designs. TrueMask is ideal for R&D exploration, bit-cell design, hot-spot analysis and mask-defect categorization that comprehends overlapping eBeam shots and dose modulation. D2S TrueMask DS is available now.
Synopsys Expands Verification IP Tools by Acquiring nSys Design Systems
Synopsys has acquired nSys Design Systems Private Limited. The deal is structured as an acquisition of substantially all the assets and employees of nSys. Other details of the acquisition have not been disclosed. nSys is an independent provider of verification IP (VIP).
Mentor Graphics Catapult C Supports Transaction Level Models Synthesis
According to Mentor Graphics, 87% of respondents in a recent survey indicated it was either mandatory or highly desirable to have high-level synthesis tools integrated with ESL flows. With that in mind, Mentor has enhanced their Catapult C high-level synthesis tool to support the synthesis of transaction level models (TLMs). TLM synthesis results in a TLM 2.0-based solution for virtual prototyping and hardware implementation, and enables the creation of synthesis-ready virtual platforms.
PrismTech Gains Model-Based Engineering, Acquires Zeligsoft Tools Unit
PrismTech[tm], a global leader in standards-based, performance-critical middleware, announced that it has acquired the tools business of Zeligsoft, a leading vendor of model-based development tools for embedded software systems. The acquisition follows on from a successful partnering agreement signed in July 2009 that created Spectra CX, which is now the most widely used SCA-compliant development tool by SDR developers. This immediate success quickly led to acquisition discussions that resulted in this announcement.
Synopsys HSPICE Precision Parallel Technology Speeds Up Simulation
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, unveiled new HSPICE® Precision Parallel (HPP) multi-threading technology that delivers up to 7X simulation speed-up for complex analog and mixed-signal designs. In addition to the new HPP technology, the HSPICE 2010 solution includes enhanced convergence algorithms, advanced analog analysis features and foundry-qualified support for process design kits (PDKs) that extend HSPICE gold-standard accuracy to the verification of complex circuits such as phase-locked loops, SERDES, data converters, high-precision custom digital and power management. With HSPICE 2010, design teams can accelerate verification of their analog circuits across process variation corners and reduce the risk of silicon respins.
OCP-IP, CircuitSutra, Imperas Announce Virtual Platform Demo
Open Core Protocol International Partnership (OCP-IP), the organization delivering a common standard for intellectual property core interfaces that facilitate “plug and play” SoC design, and CircuitSutra, experts in SystemC modeling and embedded software development, along with Imperas, the company providing the infrastructure for the future of software virtual platforms and enabling the next generation of embedded software development, announced the availability of a Virtual Platform Demo created utilizing OCP-IP’s advanced Modeling Kit. This example platform acts as a guide to OCP-IP members enabling them to quick-start their ESL activities using the OCP-IP TLM Modeling Kit; which is fully compatible with OSCI’s TLM 2.0.1. Both the kit and Virtual Platform examples are free to both OCP-IP members and non-members.
SPEculative and Exploratory Design in Systems Engineering Project
The four-year SPEEDS (SPEculative and Exploratory Design in Systems Engineering) project, funded under the European Union’s 6th Framework Programme, has come to a highly successful conclusion. The SPEEDS project has resulted in the definition of a novel end-to-end design methodology, process and tool environment for model-based safety-critical embedded systems that significantly improves design quality while reducing both design cycle times and costs.
Cadence, Fujitsu Team on Chip Package Board Co-Design Solution
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced that, with the assistance of Fujitsu Semiconductor Limited and Fujitsu VLSI Limited (hereafter collectively called Fujitsu), Cadence has developed a standardized die model that provides ASIC and microcontroller (MCU) designers with a comprehensive chip-package-board co-design solution.
Synopsys, IEEE-ISTO Form Interconnect Modeling Technical Advisory Board
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced the open source availability of its widely used Interconnect Technology Format (ITF) for parasitic modeling and the formation of a technical advisory board (TAB) under the auspices of IEEE Industry Standards and Technology Organization (IEEE-ISTO). The purpose of the Interconnect Modeling TAB (IMTAB) is to facilitate the evolution of ITF and promote an interoperable interconnect modeling format to address the industry’s advancing process technology and design needs. IMTAB founding members include representatives from industry-leading semiconductor companies, EDA companies and silicon foundries including Altera Corporation, AMD, Apache Design Solutions, GLOBALFOUNDRIES, LSI Corporation, Magma Design Automation, NVIDIA, Qualcomm, STMicroelectronics and Synopsys. Following the same model as the industry-standard Liberty[TM] library modeling format, ITF access is granted under an open source license through Synopsys’ Technology Access Program (TAP-in(SM)) and is available free of charge to anyone.
VectorCAST/C++ Features Extended Support for Renesas HEW Environment
Vector Software, the leading provider of software test tools for embedded systems, announced extended support for the Renesas High-Performance Embedded Workshop (HEW) development environment. This newest integration enables users to unit test their code and measure code coverage automatically on M16C/R8C and SuperH (SH) simulators.
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