UMC Certifies Synopsys StarRC Parasitic Extraction Solution for 28nm Process
UMC has certified Synopsys’ StarRC parasitic extraction solution for their latest 28-nanometer (nm) process technologies. UMC’s validation of StarRC extends the benefits of Synopsys’ state-of-the-art process modeling and extraction technology to UMC’s 28-nanometer customers. This enables engineers to deliver high-performance 28-nanometer devices to market with increased confidence.
Synopsys and Applied Materials Develop Technology Computer-Aided Design Models
Synopsys team with Applied Materials to create technology computer-aided design (TCAD) models for next-generation semiconductor devices. The models derived from this TCAD collaboration will enable engineers to speed up process development for 14-nanometer (nm) and 11-nm logic and new memory chip technologies. This will reduce cost and speed time-to-market.
Fujitsu Laboratories Speeds ARM Simulation by Factor of 100
Fujitsu Laboratories Limited has developed the world’s fastest simulation technology for systems using the ARM computing core, which is widely used in mobile phones and other electronic devices. Fujitsu’s simulation technology is able to faithfully reproduce hardware operations with cycle-for-cycle real-time accuracy. The technology will help reduce the development cycle for systems and devices using ARM cores and encourage the development of a greater diversity of ARM-based systems.
AWR Publishes White Paper on Visual System Simulator Co-simulating with NI LabVIEW
AWR has published a white paper. The new article is titled, AWR’s Visual System Simulator Co-simulates with NI’s LabVIEW for Enhanced Signal Processing Capabilities. The technical paper highlights how AWR’s Visual System Simulator (VSS) software and National Instruments’ (NI) LabVIEW graphical programming environment co-simulate and enable designers to analyze, optimize, and verify complex RF circuits, subsystems and digital signal processing within a unified framework.
D2S TrueMask DS Mask Wafer Double Simulation Accelerated Workstation
D2S launched the TrueMask DS mask-wafer double simulation accelerated workstation. It can help mask shops and wafer fabs with qualifying and optimizing 20nm node and below designs. TrueMask is ideal for R&D exploration, bit-cell design, hot-spot analysis and mask-defect categorization that comprehends overlapping eBeam shots and dose modulation. D2S TrueMask DS is available now.
Synopsys Expands Verification IP Tools by Acquiring nSys Design Systems
Synopsys has acquired nSys Design Systems Private Limited. The deal is structured as an acquisition of substantially all the assets and employees of nSys. Other details of the acquisition have not been disclosed. nSys is an independent provider of verification IP (VIP).
Mentor Graphics Catapult C Supports Transaction Level Models Synthesis
According to Mentor Graphics, 87% of respondents in a recent survey indicated it was either mandatory or highly desirable to have high-level synthesis tools integrated with ESL flows. With that in mind, Mentor has enhanced their Catapult C high-level synthesis tool to support the synthesis of transaction level models (TLMs). TLM synthesis results in a TLM 2.0-based solution for virtual prototyping and hardware implementation, and enables the creation of synthesis-ready virtual platforms.
PrismTech Gains Model-Based Engineering, Acquires Zeligsoft Tools Unit
PrismTech[tm], a global leader in standards-based, performance-critical middleware, announced that it has acquired the tools business of Zeligsoft, a leading vendor of model-based development tools for embedded software systems. The acquisition follows on from a successful partnering agreement signed in July 2009 that created Spectra CX, which is now the most widely used SCA-compliant development tool by SDR developers. This immediate success quickly led to acquisition discussions that resulted in this announcement.
Synopsys HSPICE Precision Parallel Technology Speeds Up Simulation
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, unveiled new HSPICE® Precision Parallel (HPP) multi-threading technology that delivers up to 7X simulation speed-up for complex analog and mixed-signal designs. In addition to the new HPP technology, the HSPICE 2010 solution includes enhanced convergence algorithms, advanced analog analysis features and foundry-qualified support for process design kits (PDKs) that extend HSPICE gold-standard accuracy to the verification of complex circuits such as phase-locked loops, SERDES, data converters, high-precision custom digital and power management. With HSPICE 2010, design teams can accelerate verification of their analog circuits across process variation corners and reduce the risk of silicon respins.
OCP-IP, CircuitSutra, Imperas Announce Virtual Platform Demo
Open Core Protocol International Partnership (OCP-IP), the organization delivering a common standard for intellectual property core interfaces that facilitate “plug and play” SoC design, and CircuitSutra, experts in SystemC modeling and embedded software development, along with Imperas, the company providing the infrastructure for the future of software virtual platforms and enabling the next generation of embedded software development, announced the availability of a Virtual Platform Demo created utilizing OCP-IP’s advanced Modeling Kit. This example platform acts as a guide to OCP-IP members enabling them to quick-start their ESL activities using the OCP-IP TLM Modeling Kit; which is fully compatible with OSCI’s TLM 2.0.1. Both the kit and Virtual Platform examples are free to both OCP-IP members and non-members.
If you are familiar with RSS feeds, you can also sign up for our free news feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
