'IP Cores' Category Archive

Evatronix NAND Flash Controller Features OCP Socket, BCH Algorithm

Posted by EDA Geek News Staff in IP Cores on Tuesday, September 2, 2008

The Silicon Intellectual Property (IP) provider, Evatronix SA, announced the latest upgrade to its highly successful NAND Flash Controller IP core. Both BCH algorithm and OCP socket further facilitate the component's implementation in various System-on-Chip (SoC) environments, as well as significantly reduce the IP core's gate count while retaining its outstanding performance. Bose, Chaudhuri, and Hocquenghem (BCH) algorithm introduces bit-level error correction for Multi Level Cell (MLC) memories, which is a significant performance improvement over Reed-Solomon code's whole word approach. Furthermore, BCH is designed to handle random scattering of errors - a typical NAND Flash feature. Due to this application-specific character, the algorithm is best suited for the newest types of memories.

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IPextreme Introduces cJTAG - IEEE 1149.7 IP Core

Posted by EDA Geek News Staff in IP Cores on Tuesday, September 2, 2008

IPextreme®, Inc., the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, announced the availability of the electronics industry's first synthesizable IP core that implements the upcoming IEEE 1149.7 standard, which will be ratified in early 2009. IEEE 1149.7 will provide designers with powerful extensions to the current IEEE 1149.1 (JTAG) standard, uses fewer pins and maintains compatibility with IEEE 1149.1-based hardware and software. The cJTAG - IEEE 1149.7 IP core, provided by IPextreme, is a configurable, ready-to-integrate semiconductor IP solution supporting all six classes of the IEEE 1149.7 standard.

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Tensilica Announces Dolby Pro Logic II, IIx Decoders for Xtensa HiFi 2

Posted by EDA Geek News Staff in IP Cores on Tuesday, August 26, 2008

Tensilica,® Inc. announced that it has added the Dolby® Pro Logic® II and Pro Logic IIx decoders to its audio codec library for Tensilica's Xtensa® HiFi 2 Audio Engine, one of the most popular commercial audio cores for system-on-chip (SOC) designs. Both Dolby Pro Logic decoders are essential sound processing technologies employed in home theater AV receivers. Dolby Pro Logic II creates a captivating 5.1-channel surround sound experience from any stereo movie, music, TV, or game audio source. Dolby Pro Logic IIx extends the sound experience up to a full 7.1-channel configuration for highly realistic, natural surround sound.

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Intel Media Processor CE 3100 Features Tensilica HiFi 2 Audio Processor

Posted by EDA Geek News Staff in IP Cores, Microcontrollers on Wednesday, August 20, 2008

At the Intel Developer Forum in San Francisco, Tensilica,® Inc. announced that the new Intel® Media Processor CE 3100 (formerly codenamed "Canmore") for Internet-connected CE devices includes Tensilica's HiFi 2 audio processor. Tensilica's HiFi 2 processor is specifically optimized to efficiently run over 50 audio software packages, including AACPlus, MP3, SRS TruSurround HD, WMA, and G.7xx Voice codecs, along with the complete suites of Dolby and DTS codecs required for set-top box and Blu-ray Disc applications.

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Mentor Graphics, Altera Team on DO-254 IP

Posted by EDA Geek News Staff in FPGAs, IP Cores on Tuesday, August 19, 2008

Supporting the growing number of avionics and military applications requiring DO-254-certifiable components, Altera Corporation (NASDAQ: ALTR) and Mentor Graphics Corporation (NASDAQ: MENT) announced the companies are working together to develop tools and methodologies for use in creating DO-254-certifiable intellectual property (IP) that targets Altera's field programmable gate array (FPGA) and HardCopy® application specific integrated circuit (ASIC) solutions. As part of this announcement, Mentor will join Altera's DO-254 Global Partner Network in order to establish design and verification best practices for DO 254-certifiable IP development and integration flows.

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Imperas to Create Free Models of MIPS Processor Cores

Posted by EDA Geek News Staff in IP Cores, Models, Simulations on Monday, August 18, 2008

Imperas announced it has signed an agreement with MIPS Technologies, Inc. (NasdaqGS: MIPS), a leading provider of industry-standard architectures, processors and analog IP for digital consumer, home networking, wireless, communications and business applications, for the verification of a series of processor models that Imperas will create and make freely available.

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