Evatronix Launches SDIO-HOST Controller IP Core
The silicon Intellectual Property (IP) provider, Evatronix SA, has announced the launching of a new SDIO-HOST Controller IP core to handle MMC and SDIO type cards and devices. The SDIO-HOST Controller is fully compatible with SD Memory version 2.00, SDIO version 2.00 and MMC version 3.31 protocols. The register set complies with SDIO Host Specification ver. 1.00 and supports an optional DMA controller as well. Up to 4 card interfaces (slots) can be utilized in complex systems, through support of the IP core's variable configuration.
Silicon Image Debuts 12MP Camera Processor IP Core for Mobile Devices
Silicon Image, Inc. (NASDAQ: SIMG), a leader in semiconductors for the secure storage, distribution and presentation of high-definition content, announced the availability of its 12 megapixel (MP) camera processor IP core for integration into system-on-a-chip (SoC) semiconductors. This technology delivers professional picture quality and advanced camera functionality once only found in digital still cameras (DSCs), but now conveniently integrated into mobile phones, portable multimedia players (PMPs), ultra mobile PCs (UMPCs) and security cameras. Versions of this technology have already been licensed by five of the world's leading mobile phone SoC suppliers.
Zensys Selects Kilopass XPM Embedded Memory for Remote Home Control
Kilopass Technology, a leading provider of semiconductor non-volatile memory (NVM) intellectual property (IP), announced that Zensys, the developer of the Z-Wave wireless home control standard, has selected the Kilopass XPM one-time programmable embedded memory technology for its broadband wireless remote home control applications. Zensys is using XPM memory to store network and application data.
Virage Logic Debuts SiWare Logic 65nm CPF ULP Standard Cell Libraries
Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner and pioneer in Silicon Aware IP(tm), announced the availability of Common Power Format (CPF) enabled 65-nanometer (nm) Standard Cell logic libraries. Virage Logic's 65nm Ultra-Low-Power (ULP) product offering will help enable customers to manage low-power design projects targeting applications in the rapidly expanding mobile consumer market which require advanced power-lowering design techniques such as power shut-down, state retention and multiple voltage islands.
eASIC Nextreme Powers Gaisler LEON3 SPARC Soft Processor
eASIC Corporation, a provider of zero-mask charge ASIC devices, announced the immediate availability of Gaisler Research's LEON3 SPARC Soft Processor. eASIC and Gaisler Research migrated the LEON3 processor to eASIC's Nextreme family of zero mask-charge ASIC devices and achieved 235MHz performance, shattering the performance achievable using high performance FPGAs. Customers now have immediate access to the LEON3 processor and GRLIB IP library for implementing single chip, SPARC V8 architecture compliant, embedded systems using Nextreme devices.
Synopsys Unveils DesignWare USB 2.0 PHY IP for 45nm Process
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, announced that its DesignWare® USB 2.0 nanoPHY is the first 45-nanometer (nm) USB 2.0 PHY intellectual property (IP) to successfully pass the USB Implementers Forum Hi-Speed USB PHY certification. Synopsys' industry-leading USB 2.0 nanoPHY mixed-signal IP, now available in the 45-nm process node, uses half the power and die area compared to previous USB PHY IP solutions and enables faster time-to-market with reduced risk.
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