Synopsys introduced an optimized version of the Dynamic Resolution Adaptation (DRA) decoder software for the DesignWare ARC Sound AS211SFX and AS221BD audio processors. The DesignWare ARC Sound DRA codec and the DesignWare ARC Sound audio processors enable OEMs and SoC designer to develop HD audio for Chinese consumer electronic products. The optimized version of the DesignWare ARC Sound DRA decoder will be generally available in July 2011 (available for early access customers now).
Cadence Design Systems introduced a new DDR4 IP solution, which consists of hard and soft PHY IP, controller IP, memory models, verification IP, tools and methodologies, and signal integrity reference designs for the package and board. The Cadence DDR4 IP solution speeds integration, reduces cost and ensures design manufacturability. DDR4 controller IP, verification IP and memory models are available now. The DDR4 specification features speeds ranging from 1600 mega transfers per second (MT/s) up to 3200 MT/s (over 50% faster than the current DDR3 standard).
MIPS Technologies will offer an IP core that combines a 64-bit processor architecture with simultaneous multi-threading (SMT) technology. Code named Prodigy, the IP family enables engineers to quickly and easily develop MIPS64 solutions at a fraction of the cost and time it would take to develop a 64-bit core themselves. The 64-bit core will be available later this year.
Mentor Graphics Corporation (NASDAQ: MENT) announced it has teamed up with ARM to provide an automated memory test and repair solution for ARM embedded memories and processor cores. The new capability provides full interoperability between Mentor’s industry-leading Tessent[TM] memory test and repair solution and ARM’s family of cores and embedded memory IP.
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Synopsys’ DesignWare® High-Definition Multimedia Interface[tm] (HDMI[tm]) 1.4a Transmitter (Tx) digital controller and PHY IP solutions in the 40-nanometer (nm) process node have achieved certification from an HDMI Authorized Training Center (ATC). The DesignWare HDMI PHY IP achieved HDMI 1.4a compliance by passing all process, voltage and temperature variation tests, which are key certification requirements for environmental robustness. Synopsys’ fully compliant HDMI 1.4a Tx solution is now available in more than 10 process technologies, ranging from 90-nm to 40-nm. With support for the latest HDMI 1.4a specification features such as all eight 3D formats, HDMI Ethernet and Audio Return Channel (HEAC) and real-time content signaling, the DesignWare HDMI 1.4a Tx controller and PHY IP enable system-on-chip (SoC) designers and device manufacturers to quickly incorporate advanced functionality into their multimedia source applications with less risk and improved time-to-market.
ARM and Semiconductor Manufacturing International Corporation (“SMIC”, NYSE: SMI and HKSE: 981) announced an agreement to collaborate on the development of ARM leading physical IP library platform for SMIC 65nmLL and 40nm LL technology process nodes. This agreement will provide free access on the ARM DesignStart[tm] online IP access portal to library suites of 9-track and 12-track multi-Vt logic libraries, power management kits, ECO kits and ARM high density optimized memory compilers. The agreement extends the longstanding partnership to provide their mutual customers with highly differentiated IP on a variety of process technologies including 180 nm, 130nm, 110nm and 90nm.
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced it is providing its customers an optimized implementation methodology for the new ARM® Cortex[tm]-A15 MPCore[tm] processor that enables them to start designing Cortex-A15 processor-based SoCs immediately. As ARM developed the Cortex-A15 MPCore processor – its most advanced processor for mobile, consumer and infrastructure applications – Cadence® worked alongside the microprocessor IP leader to develop the methodology for customers seeking early access to this cutting-edge ARM processor technology for Silicon Realization.
Open-Silicon, Inc., MIPS Technologies, Inc. (NASDAQ: MIPS), and Dolphin Technology announced the successful tapeout of a high-performance ASIC processor at over 2.4GHz under typical conditions. This achievement, as measured in timing closure against TSMC reference flow signoff conditions, will make this one of the highest frequency ASIC processors ever built, highlighting the companies’ industry-leading technologies for building high-performance processor-based systems. This high-performance ASIC processor is a follow-on test chip to the 65nm, 1.1GHz test chip announced by Open-Silicon and MIPS Technologies at the end of last year.
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Synopsys’ DesignWare® Serial Advanced Technology Attachment (SATA) IP solution has successfully passed the SATA International Organization (SATA-IO) electrical, digital and system interoperability testing for 130- to 40-nanometer (nm) process technologies. The SATA-IO interoperability testing validates Synopsys’ internal testing of the DesignWare SATA IP, which includes extensive digital and mixed-signal simulation validation, hardware FPGA-based prototyping using Synopsys’ HAPS® solution, and PHY test chip silicon characterization.
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced immediate availability of the DesignWare® MIPI M-PHY® IP for next-generation high-speed interfaces based on the newly ratified MIPI® Alliance M-PHY specification. With this latest addition to the DesignWare MIPI IP portfolio, Synopsys is the first provider to offer a comprehensive solution of a controller and PHY IP for both the MIPI DigRF(SM) v3 (2.5G/3.0G) and v4 (4G) standards. Incorporating both standards in a mobile device brings the benefit of the faster 4G standards while preserving broad coverage by using 2.5G/3.0G as a fallback mode. The configurable MIPI DigRF V4 Master Controller and M-PHY hard macro are compliant to the MIPI Alliance specifications. Utilizing a single-vendor solution enables designers to lower the risk and cost of integrating these MIPI interfaces into baseband and application processor integrated circuits (ICs), speeding time-to-market of advanced semiconductor solutions for LTE and Mobile WiMAX.