The DSMART IP Core combines reduced CPU utilization and small size to handle many smart card reader application tasks. It is based on ISO 7816-3/EMV4.2 requirements with hardware support for T0 character oriented protocol and T1 block oriented protocol.
The display interface provides a MIPI DSI bridge from the processor to an embedded DisplayPort LCD at 30 percent higher bandwidth than competing devices. The SN65DSI86 will be demonstrated at the Consumer Electronics Show in 2014.
Accellera Systems Initiative has developed new vendor extensions for IEEE 1685-2009: IP-XACT, Standard Structure for Packaging, Integrating and Reusing IP within Tool Flows. IP-XACT enabled IP is leveraged by a wide range of companies. The vendor extensions reinforce Accellera’s commitment to shape IP standards that promote reuse and speed designer productivity substantially.
Cadence Design Systems plans to acquire the IP business of Evatronix SA SKA. The acquisition is expected to close in the second quarter of 2013, and is not expected to have a material impact on Cadence’s balance sheet or second quarter or fiscal 2013 results of operations. Terms of the transaction were not disclosed.
ARM and Cadence Design Systems teamed on the first ARM Cortex-A57 processor for TSMC’s 16-nanometer (nm) FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros. Their joint innovations will enable engineers to accelerate product development cycles and take advantage of leading-edge processes and IP.
Cadence Design Systems acquired Tensilica for about $380 million in cash. Tensilica is a leader in dataplane processor IP core licensing with over 200 licensees. Tensilica’s configurable dataplane processing units are optimized for embedded data and signal processing. The IP cores are ideal for mobile wireless, network infrastructure, auto infotainment and home applications. As of December 31, 2012, Tensilica had approximately $30 million in cash.
Cadence Design Systems has acquire Cosmic Circuits. The IC and Systems business of Cosmic Circuits will be spun off into a separate new company to be owned by certain existing shareholders of Cosmic Circuits. The acquisition is expected to close in 30 to 60 days, and is not expected to have a material impact on Cadence’s 2013 results of operations. Terms of the transaction were not disclosed.
Cadence Design Systems’ design IP portfolio now includes intellectual property for the LPDDR3 mobile memory standard. As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption. In addition to LPDDR3, Cadence offers IP for other mobile and non-mobile memory standards in high demand by SoC designers, including Wide I/O and DDR4.
Synopsys and Arteris recently teamed on a joint analog and digital IP solution to implement the MIPI Alliance Low Latency Interface (LLI) 1.0 specification. The early integration and availability of the Arteris and Synopsys solution helps speed time to market for MIPI LLI adopters. Arteris and Synopsys’ joint MIPI LLI IP solution is available now for select early access customers. System hardware implementing the joint solution will be available in the second half of 2012.
Synopsys’ DesignWare 96 dB Hi-Fi Audio IP has achieved first-pass silicon success in 65-nanometer (nm) and 55-nm process technologies for multiple foundries. The silicon-proven audio IP is ideal for consumer electronic system-on-chip (SoC) applications such as portable media players, smart phones, CD/DVD/ Blu-Ray Disc players/recorders, digital TV and digital cameras. The Synopsys DesignWare 96 dB Hi-Fi Audio IP in 65-nm and 55-nm processes is available now for multiple foundries.