Cadence Design Systems Acquires Evatronix’s IP Business
Cadence Design Systems plans to acquire the IP business of Evatronix SA SKA. The acquisition is expected to close in the second quarter of 2013, and is not expected to have a material impact on Cadence’s balance sheet or second quarter or fiscal 2013 results of operations. Terms of the transaction were not disclosed.
Cadence, ARM Team on Cortex-A57 64-bit Processor for TSMC 16nm FinFET Process
ARM and Cadence Design Systems teamed on the first ARM Cortex-A57 processor for TSMC’s 16-nanometer (nm) FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros. Their joint innovations will enable engineers to accelerate product development cycles and take advantage of leading-edge processes and IP.
Cadence Acquires Tensilica for $380 Million
Cadence Design Systems acquired Tensilica for about $380 million in cash. Tensilica is a leader in dataplane processor IP core licensing with over 200 licensees. Tensilica’s configurable dataplane processing units are optimized for embedded data and signal processing. The IP cores are ideal for mobile wireless, network infrastructure, auto infotainment and home applications. As of December 31, 2012, Tensilica had approximately $30 million in cash.
Cadence Design Systems Acquires Cosmic Circuits, Broadens IP Portfolio
Cadence Design Systems has acquire Cosmic Circuits. The IC and Systems business of Cosmic Circuits will be spun off into a separate new company to be owned by certain existing shareholders of Cosmic Circuits. The acquisition is expected to close in 30 to 60 days, and is not expected to have a material impact on Cadence’s 2013 results of operations. Terms of the transaction were not disclosed.
Cadence Announces LPDDR3 Memory IP Solution
Cadence Design Systems’ design IP portfolio now includes intellectual property for the LPDDR3 mobile memory standard. As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption. In addition to LPDDR3, Cadence offers IP for other mobile and non-mobile memory standards in high demand by SoC designers, including Wide I/O and DDR4.
Synopsys, Arteris Team on IP Solution for MIPI Alliance Low Latency Interface
Synopsys and Arteris recently teamed on a joint analog and digital IP solution to implement the MIPI Alliance Low Latency Interface (LLI) 1.0 specification. The early integration and availability of the Arteris and Synopsys solution helps speed time to market for MIPI LLI adopters. Arteris and Synopsys’ joint MIPI LLI IP solution is available now for select early access customers. System hardware implementing the joint solution will be available in the second half of 2012.
First-Pass Silicon Success: Synopsys DesignWare 96 dB Hi-Fi Audio IP
Synopsys’ DesignWare 96 dB Hi-Fi Audio IP has achieved first-pass silicon success in 65-nanometer (nm) and 55-nm process technologies for multiple foundries. The silicon-proven audio IP is ideal for consumer electronic system-on-chip (SoC) applications such as portable media players, smart phones, CD/DVD/ Blu-Ray Disc players/recorders, digital TV and digital cameras. The Synopsys DesignWare 96 dB Hi-Fi Audio IP in 65-nm and 55-nm processes is available now for multiple foundries.
Synopsys DRA Decoder for DesignWare ARC Sound Audio Processors
Synopsys introduced an optimized version of the Dynamic Resolution Adaptation (DRA) decoder software for the DesignWare ARC Sound AS211SFX and AS221BD audio processors. The DesignWare ARC Sound DRA codec and the DesignWare ARC Sound audio processors enable OEMs and SoC designer to develop HD audio for Chinese consumer electronic products. The optimized version of the DesignWare ARC Sound DRA decoder will be generally available in July 2011 (available for early access customers now).
Cadence DDR4 IP Solution
Cadence Design Systems introduced a new DDR4 IP solution, which consists of hard and soft PHY IP, controller IP, memory models, verification IP, tools and methodologies, and signal integrity reference designs for the package and board. The Cadence DDR4 IP solution speeds integration, reduces cost and ensures design manufacturability. DDR4 controller IP, verification IP and memory models are available now. The DDR4 specification features speeds ranging from 1600 mega transfers per second (MT/s) up to 3200 MT/s (over 50% faster than the current DDR3 standard).
MIPS Prodigy 64-Bit Multi-threaded Multiprocessor IP Core
MIPS Technologies will offer an IP core that combines a 64-bit processor architecture with simultaneous multi-threading (SMT) technology. Code named Prodigy, the IP family enables engineers to quickly and easily develop MIPS64 solutions at a fraction of the cost and time it would take to develop a 64-bit core themselves. The 64-bit core will be available later this year.
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