Lawrence Berkeley National Laboratory, Tensilica Team on Supercomputing
Tensilica®, Inc. and the U.S. Department of Energy's Lawrence Berkeley National Laboratory announced a collaboration program to explore new design concepts for energy-efficient high-performance scientific computer systems. The joint effort is focused on novel processor and systems architectures using large numbers of small processor cores, connected together with optimized links, and tuned to the requirements of highly-parallel applications such as climate modeling. These demanding scientific problems require 100 to 1000 times higher computation throughput than today's high-end computing installations, but conventional systems require so much electricity, generate so much heat, and require such complex physical installations that the costs would be prohibitive. This collaboration in application-directed supercomputing aims at making "exascale systems" (up to one quintillion floating point operations per second) feasible and cost-effective.
Xtensa HiFi 2 Audio Engine Codec Library Gains Dolby TrueHD Decoder
Tensilica,® Inc. announced that it has added the Dolby® TrueHD decoder to its audio codec library for Tensilica's Xtensa® HiFi 2 Audio Engine, one of the most popular commercial audio cores for system-on-chip (SOC) designs. Dolby TrueHD is the ultimate high-definition audio experience for next-generation entertainment, delivering warm, realistic and enveloping sound from the Blu-ray Disc(tm) format.
TranSwitch Develops first 10.5 Gbps HDMI 1.3 PHY IP Core
TranSwitch® Corporation (NASDAQ: TXCC), a leading provider of carrier-class semiconductor solutions for the converging voice, data and video network, announces the first HDMI® 1.3 Intellectual Property (IP) cores operating at up to 10.5 Gbps (3.5Gbps per channel). The HD-PXL-1.3 transmitter IP core extends TranSwitch's existing offerings in high-performance video interconnect applications and is available in 90 nm CMOS technology.
Synopsys Introduces DesignWare PHY IP for 5.0 Gbps PCI Express 2.0
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, announced the availability of the DesignWare PHY IP for PCI Express 2.0 (Gen II), based on the PCI Express 2.0 base specification. This product release further extends Synopsys' IP leadership by providing designers with the IP industry's only complete, silicon-proven PCI Express 2.0 IP solution, including digital controllers, PHY and verification IP from a single vendor. Accessing all the IP from one provider allows designers to lower the risk and cost of integrating the 5.0 Gbps PCI Express interface into their high performance system-on-chip (SoC) designs.
Virage Logic Intelli DDR Memory Controller Interface Improves Efficiency
Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner and pioneer in Silicon Aware IP(tm), announced that the Intelli(tm) Double Data Rate (DDR) memory controller interface can provide up to a 20 percent efficiency gain for high-performance applications, while still maintaining low-power. Architected from the ground up to provide a combination of low-latency, high-performance and low-power options, the Intelli DDR solution incorporates intelligent scheduling algorithms for superior system bandwidth.
Northwest Logic Debuts PCI Express 2.0 Solution for Xilinx Virtex-5FXT
Northwest Logic announced the immediate availability of a high-performance, hardware-proven PCI Express® 2.0 solution for Xilinx's Virtex®-5 FXT platform. This solution combines Northwest Logic's full-featured PCI Express 2.0 Core (5Gbit/s), a high-performance, on-demand, multi-engine DMA Back-End Core, DMA Driver (Windows or Linux) and PCI Express GUI to provide a complete, pre-packaged PCI Express 2.0 solution. The solution enables high-performance, multi-DMA engine PCI Express 2.0 designs to be quickly developed for the Virtex-5FXT FPGAs.
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