'FPGAs' Category Archive

Dini Group Selects Altera Stratix III for FPGA-Based Prototyping Board

Posted by EDA Geek News Staff in FPGAs on Monday, November 10, 2008

Altera Corporation (NASDAQ:ALTR) announced The Dini Group selected the Stratix® III EP3SL340 FPGA, featuring 340K logic elements (LEs), in its DN7020K10, the industry's largest single-board FPGA-based prototyping engine. The DN7020K10 supports 20 EP3SL340 FPGAs in 1,760-pin packages providing 1,104 user I/Os per device and a capacity of more than 50 million equivalent ASIC gates. Customers designing custom ASICs, such as those used in wireless communications, networking and graphics-processing applications, can use this ultra-high-capacity prototyping board to verify their logic designs and run them at near real-time clock speeds.

Read more »

Tokyo Electron Device Unveils of 3 inrevium FPGA PCI Express Platforms

Posted by EDA Geek News Staff in EDA Tools, FPGAs on Monday, November 10, 2008

Tokyo Electron Device Limited (TED) has announced the release of three inrevium Virtex®-5 High-Density PCI Express Platforms. These PCI Express Gen 1 & 2 capable platforms utilize Xilinx Virtex-5 LX330T, SX240T and FX200T FPGAs, the highest density FPGAs available. "In recent years, high performance embedded systems require FPGAs with higher speed, density and performance," said Yasuo Hatsumi, Director and Xilinx Product Manager, PLD Solution Division of TED. "Further, with shorter product life cycles, customers demand FPGA evaluation platforms that are flexible and meet diversified needs."

Read more »

Aldec Mixed-Language HDL Simulator to Support OVM 2.0

Posted by EDA Geek News Staff in EDA Tools, FPGAs on Monday, November 10, 2008

Aldec, Inc., a leader in mixed-language HDL simulation for ASIC and FPGA devices, is pleased to announce that it is now an official partner on OVM World, the community site for the Open Verification Methodology (OVM). This partnership will enable Aldec to offer support for OVM 2.0, the first open, language-interoperable verification methodology, co-developed by Cadence Design Systems, Inc. (NASDAQ: CDNS). This OVM-based release of the Aldec mixed-language HDL simulator will provide the OVM community additional choices and further reinforce the value of a widely supported open-source methodology. Aldec plans to integrate OVM 2.0 into its common-kernel, mixed-language, HDL simulator on the Windows® and Linux® 32/64 platforms.

Read more »

Northwest Logic Debuts x8 PCI Express 2 Solution for Virtex-5 FXT FPGA

Posted by EDA Geek News Staff in FPGAs, IP Cores on Monday, November 10, 2008

Northwest Logic announces the immediate availability of a high-performance, hardware-proven x8 PCI Express® 2.0 Solution for Xilinx's Virtex®-5 FXT FPGA platform. This solution combines Northwest Logic's full-featured x8 PCI Express 2.0 cores and software to provide a complete, pre-packaged x8 PCI Express 2.0 solution. The solution enables high-performance x8 PCI Express 2.0 designs to be quickly developed for Virtex-5 FXT FPGAs.

Read more »

Real Intent Releases Meridian FPGA Verification Software

Posted by EDA Geek News Staff in EDA Tools, FPGAs on Tuesday, November 4, 2008

Real Intent Inc., the leading supplier of verification software for electronic design, announced its first release of Meridian FPGA[tm] verification software. Meridian FPGA is specifically designed to work with Altera Corporation's latest release of its Quartus® II software, version 8.1, to verify Clock Domain Crossings (CDC). It offers a cost-effective alternative when compared to the cost of equivalent ASIC design software.

Read more »

Altera Announces Quartus II Software 8.1

Posted by EDA Geek News Staff in EDA Tools, FPGAs on Monday, November 3, 2008

Reaffirming its leadership position in performance and productivity for CPLD, FPGA, and HardCopy® ASIC designs, Altera Corporation (NASDAQ:ALTR) unveiled Quartus® II software version 8.1. This latest release of Quartus II software continues the company's history of delivering high-density FPGA compile times three times faster than other FPGA-vendor supplied development software, based on internal benchmarks. The enhanced productivity features within Quartus II software enable design teams to close timing and power faster, lower R&D costs and shorten time to market.

Read more »

If you found this page useful, bookmark and share it on:
 
EDA Geek Newsletter
Don't have time to visit EDA Geek everyday? Then sign up for our free newsletter. We'll send you an email when we have something to share with you. Your email address will be kept confidential and we will not share, sell, or rent it to anyone. You can unsubscribe at any time by clicking a link in the email.

Enter your email address to sign up for our free newsletter:   

If you are familiar with RSS feeds, you can also sign up for our free news feed. Our RSS feed is updated in real-time while our newsletter is updated daily.