EDA Geek » FPGAs

SpaceStudio Virtual Platform Technology Supports ARM-based FPGA Design

Ken Cheung — Tue, 01 Nov 2011 19:04:16 +0000

Space Codesign® Systems announced the support for ARM-based FPGA design in its SpaceStudio^TM 2.2 virtual platform technology. Pioneering hardware/software codesign technology enables electronic engineers to enjoy a higher level of abstraction and executable representation for embedded systems design in commercial multimedia applications. System architects and design engineers can now efficiently exploit the high performance ARM Cortex-A9 dual MPCore, and easily define which code can be moved from hardware to software using sophisticated hardware/software partitioning based on their needs.

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S2C Experienced Strong 2010, Expects Record Year in 2011

Ken Cheung — Tue, 08 Mar 2011 05:28:22 +0000

S2C announced it has experienced very strong growth in 2010. According to S2C, 2011 is shaping up to be another record year. “I am very pleased with the number of repeat customers like Acton Semiconductor that we are seeing,” stated Mon-Ren Chene, Chairman and CTO of S2C. “This validates that we are continuing to deliver value to our customers. We are focused on growing our rapid FPGA prototyping infrastructure but adding Prototype Ready[TM] accessories, IP and platforms.”

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Altera Extends OTN IP Portfolio by Acquiring Avalon Microelectronics

Ken Cheung — Tue, 14 Dec 2010 16:53:40 +0000

Altera Corporation (Nasdaq: ALTR) announced it has acquired Avalon Microelectronics Inc., an industry leader in flexible Optical Transport Network (OTN) IP, for use in its FPGA and ASIC products. With the acquisition of Avalon, Altera expands its portfolio of customizable IP solutions for OTN applications, supporting data rates at 1.2G, 2.5G and 10G, as well as 40G and 100G.

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Silicon Labs, Xilinx Team on Solutions for Digital Broadcast Video

Ken Cheung — Tue, 14 Sep 2010 11:07:22 +0000

Silicon Laboratories Inc. (NASDAQ: SLAB), a leader in high-performance, analog-intensive, mixed-signal ICs, announced support for a range of Xilinx development platforms that increase flexibility and performance in applications such as digital broadcast video. Xilinx, a leader in complete programmable logic solutions, leverages Silicon Labs’ frequency-flexible timing IC solutions in a number of its latest development platforms, including the new Spartan-6 FPGA Broadcast Connectivity Kit, where Silicon Labs’ low jitter technology maximizes link integrity.

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RFEL Extends Wideband Digital Down Converter IP Core to 1 GHz

Ken Cheung — Tue, 20 Jul 2010 11:28:29 +0000

RF Engines Limited (RFEL) has extended the range of its Digital Down Converter (DDC) technology so that it can now process up to 1 GHz of bandwidth (2Gsps ADC rate) input and provide a narrower band output. This technology can operate with fixed frequencies and bandwidths or be fully flexible as required. One of the main application areas is for Electronic Surveillance in military digital receivers, where this approach enables a desired signal band to be extracted from a wide slice of the spectrum in order that further analysis of the signal content can be carried out.

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Actel Qualifies RT ProASIC3 FPGA Family for Space Flight Systems

Ken Cheung — Tue, 20 Jul 2010 11:03:08 +0000

Reaffirming its leadership in the space market, Actel Corporation (Nasdaq: ACTL) announced the first fully qualified flash based FPGAs for space flight applications. Actel’s RT ProASIC®3 family successfully passed the extensive testing required for MIL-STD-883 Class B qualification. Building on its 17 year heritage and leadership of providing antifuse FPGAs for system critical applications, Actel ushers in a new paradigm in the space market with the qualification of its flash-based RT ProASIC3 devices.

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Actel RTAX-DSP FPGA Devices Qualify for MIL-STD-883 Class B

Ken Cheung — Mon, 19 Jul 2010 19:05:46 +0000

Actel Corporation (Nasdaq: ACTL) announced that its radiation-tolerant RTAX-DSP FPGAs have completed qualification in accordance with the military and aerospace industry standard MIL-STD-883 Class B specification. This qualification expands Actel’s support of high-speed signal processing applications for space payloads and exemplifies its ongoing innovation and commitment to serve designers of spaceflight systems.

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Lattice Offers 90+ Reference Designs for MachXO, ispMACH 4000ZE PLDs

Ken Cheung — Mon, 19 Jul 2010 17:19:51 +0000

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced that it has released more than 90 reference designs optimized for the MachXO[tm] and ispMACH® 4000ZE PLDs. Reference designs enable the quick and efficient design and deployment of commonly used functions such as general purpose I/O expander, I2C bus master / slave, LCD controller and SD Flash controller, as well as other interfaces, in a variety of markets including consumer, communications, computing, industrial and medical. The reference designs, coupled with complete documentation and design source code, are fully customizable and enable designers to reduce design time, boost productivity and accelerate time-to-market.

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Hella Aglaia Selects Impulse C to FPGA Xilinx FPGAs for 3D Passenger

Ken Cheung — Wed, 20 Jan 2010 12:06:52 +0000

Impulse Accelerated Technologies announced that Hella Aglaia has completed a design for a Hella Aglaia computer vision 3D automatic passenger counting system using Impulse C to FPGA tools and Xilinx FPGAs in an ASIC prototyping flow. Based on 3D-Sense Technology Hella Aglaia’s self contained Automatic Passenger Counting System AVC 1 offers a counting accuracy greater than 98%. It is possible to verify all results at any time, through the comparison with video recordings.

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Xilinx Debuts 6 New Virtex-6 FPGA and Spartan-6 FPGA Development Kits

Ken Cheung — Tue, 08 Dec 2009 18:53:48 +0000

Xilinx, Inc. (Nasdaq: XLNX) announced six new development kits as part of its Targeted Design Platforms for enabling developers to focus on innovation and differentiation when designing with FPGAs. These development platforms for the Virtex®-6 and Spartan®-6 families significantly shorten the time it takes to reach optimal levels of system performance, while ensuring low levels of power consumption during system-on-chip (SoC) development. The new kits target embedded processing, DSP and the building of systems that require high-speed serial connectivity by providing design teams with optimized tool suites tuned to their design flow, fully functional IP, and Targeted Reference Designs common to their areas of expertise.

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Vanguard Software Solutions Becomes Member of Xilinx Alliance Program

Ken Cheung — Tue, 17 Nov 2009 12:02:34 +0000

Vanguard Software Solutions, Inc. (VSOFTS), a recognized leader in development of video coding products and technologies, has joined the Xilinx Alliance Program as a supplier of AVC Encoder IP Core solutions. As of the date of this press release, VSOFTS has made available its highly flexible AVC-Intra Encoders and CABAC Encoder/Decoder IP Cores for Xilinx® Virtex® FPGA and Spartan® FPGA-based solutions to Xilinx FPGA customers. These IP Cores are optimized for the Virtex architecture, and designed to provide the highest level Broadcast quality compression in a compact, low power design.

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Xilinx Simplifies Power Design with TI Digital Power Management

Ken Cheung — Mon, 31 Aug 2009 16:39:26 +0000

Texas Instruments (TI) (NYSE: TXN) announced Xilinx is using TI power management technology to simplify power design in its new Virtex(R)-6 ML605 field programmable gate array (FPGA) evaluation kit. TI’s Fusion Digital Power(TM) controllers give FPGA users advanced power management capability and design flexibility, including the ability to monitor a power system’s behavior in real time.

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EDA/SOPC Lab Opens at Peking University School of Software and Microelectronics

Ken Cheung — Tue, 11 Aug 2009 21:14:32 +0000

Altera Corporation (NASDAQ:ALTR) announced the opening of the new Peking University and Altera International Limited Joint EDA/SOPC Lab at the Peking University School of Software and Microelectronics (Wuxi), Jiangsu Province, China. This is the 66th Joint Lab and Training Center (JLTC) that Altera has established with major universities in China. As part of Altera’s worldwide University Program, the JLTCs are equipped with the latest Altera® Quartus® II design software and a set of Altera DE2-70 development kits to aid professors in conducting hands-on training with students.

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Xilinx Virtex-5 FPGA Powers Vulcan SP HT6210 Network Interface Card

Ken Cheung — Fri, 31 Jul 2009 10:29:10 +0000

Commex Technologies Ltd., a provider of intelligent, high-performance data-routing solutions for x86 multicore systems, revealed that its Vulcan SP HT6210 Network Interface Card (NIC) has achieved data throughput of 27 Gbps. The Commex NIC accomplishes this unparalleled bandwidth by maximizing the performance of its onboard Xilinx® Virtex®-5 FPGA, and by leveraging the board’s 16-lane, 1.2Gtps HyperTransport bus interface.

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Icera Espresso 300 3G Soft Modem Features QuickLogic ArcticLink CSSP

Ken Cheung — Thu, 30 Jul 2009 16:38:34 +0000

QuickLogic Corporation (NASDAQ: QUIK), the lowest power programmable solutions leader, announced the selection of its Customer Specific Standard Product (CSSP), based on the ArcticLink solution platform, for the Icera Espresso® 300 3G soft modem platform, that is now entering production. Icera is a leader in software-defined wireless chipsets and is the only company to deliver software-based cellular modems for broadband data cards, USB sticks, and mobile internet devices. Icera’s reference design uses a wafer-level chip scale (WLCSP) version of the ArcticLink solution platform to compliment its second-generation baseband chip design. QuickLogic provides higher speed, smart data transfers between USB and SD/SDHC memory via QuickLogic’s innovative Smart Programmable Integrated Data Aggregator (SPIDA) system block.

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Cadence, Xilinx Team on Verification for FPGA Targeted Design Platforms

Ken Cheung — Wed, 24 Jun 2009 21:03:26 +0000

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it has teamed with Xilinx to enable delivery of encrypted simulation models of Xilinx intellectual property (IP) in the latest 11.2 release of the Xilinx ISE Design Suite. The result is an expanded library of design IP and complementary simulation models supported by the Cadence® Incisive® functional verification platform for the new Xilinx Base Targeted Design Platform. Used in conjunction with the Open Verification Methodology (OVM) to provide multi-language verification and reuse, this approach can help mutual customers reduce risk and boost schedule predictability and quality.

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Actel Cup China Students FPGA Design Competition Winners

Ken Cheung — Wed, 27 May 2009 22:50:52 +0000

Actel Corporation (Nasdaq: ACTL), the leader in low-power and mixed-signal FPGAs, announced the winners of its 2009 Actel Cup China Students FPGA design competition. Chosen from more than 300 submissions by students from 190 universities, designs from Xian University of Electronic Science and Technology and South China Agricultural University were tied for first place, meeting the contest’s very high standards for creativity, including three key qualifications: high level of innovation, immediate market viability and easy system implementation. This year’s competition was co-sponsored with Guangzhou ZLGMCU Development Company (ZLGMC).

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Achronix Announces Encryption Standard IP Cores for Speedster

Ken Cheung — Wed, 06 May 2009 23:35:46 +0000

Achronix Semiconductor, maker of the world’s fastest field-programmable gate arrays (FPGAs), announced the availability of new, high-performance Advanced Encryption Standard (AES) IP cores for its Speedster[TM] 1.5 GHz family. These high-performance 128-bit key size AES cores, from Portland, Ore.-based Signali Corp., are targeted at 10 Gbps, 40 Gbps, and 100 Gbps applications. They demonstrate the speed of the Speedster FGPA fabric, as well as the balance between throughput performance and resource minimization achieved by the Signali Cores.

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Tokyo Electron Device Unveils inrevium TB-5V-SX95T4-HSC FPGA Platform

Ken Cheung — Wed, 18 Mar 2009 15:47:25 +0000

Tokyo Electron Device Limited (TED) has announced the release of Quad Virtex-5 FPGA High-Speed Computing Platform. The inrevium TB-5V-SX95T4-HSC features four Xilinx Virtex-5 SX95T FPGAs and can realize high-speed and more complex processing (multiple data parallel processing).

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Actel Debuts SoftConsole 2.2 Embedded Software Development Environment

Ken Cheung — Mon, 16 Mar 2009 15:50:10 +0000

Actel Corporation (Nasdaq: ACTL) announced the availability of SoftConsole version 2.2, the next-generation free development environment for embedded design. This new version includes enhanced capabilities for debug and the downloading of programs, including a new flash loader, and support for the Microsoft® Vista operating system. Leveraging Actel’s IGLOO® low-power FPGAs and Actel Fusion® mixed-signal FPGAs, SoftConsole is a single programming environment that enables software engineers to write and debug C and C++ programs targeted at Actel’s portfolio of embedded processors, including ARM® Cortex[tm] -M1 and Core8051s.

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Actel Introduces Fusion Embedded Development Kit

Ken Cheung — Mon, 09 Mar 2009 15:40:25 +0000

Continuing to demonstrate the integration benefits that mixed-signal FPGAs offer, Actel Corporation (Nasdaq: ACTL) announced the Fusion Embedded Development Kit, enabling system designers to quickly and cost effectively prototype a full system-on-a-chip design. The kit features the Actel Fusion® mixed-signal FPGA, the only one of its kind in the industry, and supports a variety of processors, including license-free versions of the ARM® Cortex(TM)-M1 and Core8051.

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MSC Vertriebs Unveils Hpe_IRP Reference Design for Industrial Automation

Ken Cheung — Fri, 06 Mar 2009 15:33:26 +0000

MSC Vertriebs GmbH announced the modular and flexible reference design platform Hpe®_IRP for industrial automation applications based on the Intel® Atom[tm] processor and Altera Arria GX FPGA. This platform has been developed using technologies from Gleichmann Electronics Research GmbH & Co KG, Intel Corporation, Altera Corporation and 3S-Smart Software Solutions GmbH. The development kit provides designers with a solution for immediately starting designs enabling field bus and real-time Ethernet connectivity in an industrial run-time environment. Target markets for the reference platform are industrial automation applications such as programmable logic controllers (PLCs), human machine interfaces (HMIs), panel PCs, and industrial drives.

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Lattice Semiconductor Unveils Programmable PCI Express-to-HSS Bridge

Ken Cheung — Mon, 02 Mar 2009 15:50:12 +0000

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the availability of a low cost programmable PCI Express-to-High Speed Serial (HSS) bridge for the CAP12-120, a Small Office Home Office (SOHO) Voice Over IP (VOIP) platform running on Intel® architecture. This bridge design has been implemented in the award-winning LatticeECP2M[tm] FPGA. The solution utilizes the LatticeECP2M’s low power, high-performance SERDES and a Lattice PCI Express Intellectual Property (IP) core.

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Xilinx to Demonstrate, Present at Embedded World 2009

Ken Cheung — Wed, 25 Feb 2009 15:47:35 +0000

Xilinx, Inc. (Nasdaq: XLNX) announced its participation at Embedded World 2009 in Nuremberg, Germany from March 3 through 5. The company will demonstrate and present advanced embedded processing technologies that deliver enhanced system-level performance, design flexibility, and increased productivity for a broad range of applications in areas such as industrial automation, automotive driver assistance, and infotainment.

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Sundance Unveils SMT712 Dual DAC PXI Express Hybrid Peripheral Module

Ken Cheung — Tue, 24 Feb 2009 17:58:32 +0000

Sundance, the leading supplier and manufacturer of advanced digital signal processing (DSP) and reconfigurable FPGA solutions, announced the expansion of its multiprocessor PXI Express offering with the immediate availability of its SMT712 Dual DAC PXI Express Hybrid Peripheral Module. The SMT712 module is a dividend of the Sundance PXI product development roadmap that was announced in October 2008. It demonstrates the Company’s ongoing commitment and investment in the PXI open specification and brings extreme FPGA acceleration to PXI Express systems.

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Lattice Launches PAC-Designer 5.0 Mixed Signal Design Tool Suite

Ken Cheung — Mon, 23 Feb 2009 17:33:03 +0000

Lattice Semiconductor (NASDAQ: LSCC) announced Version 5.0 of its PAC-Designer® mixed signal design tool suite with new device support and improved quality of results. The PAC-Designer 5.0 software now supports the new ispClock[tm]5400D family of in-system programmable ICs, which are ideal for applications that require low-cost SERDES clock references and distributing high speed differential clocks.

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Lattice Debuts Service Pack 1 for ispLEVER v7.2 FPGA Design Tool Suite

Ken Cheung — Mon, 23 Feb 2009 17:15:14 +0000

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the immediate availability of Service Pack 1 for Version 7.2 of its ispLEVER® FPGA design tool suite. The release adds support for the new LatticeECP3[tm] FPGA family and the latest release of Synopsys’ Synplify Pro® advanced FPGA synthesis for all operating systems supported and Aldec’s Active-HDL[tm] Lattice Edition simulator for Windows.

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Lattice Rolls Out ispClock 5400D Differential Clock Distribution ICs

Ken Cheung — Mon, 23 Feb 2009 16:56:45 +0000

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced its ispClock[tm]5400D family of differential clock distribution ICs, featuring the CleanClock[tm] ultra-low phase noise PLL. The ispClock5400D family contains the six-output ispClock5406D and ten-output ispClock5410D. The FlexiClock[tm] output section of the ispClock5400D devices supports multiple logic standards and dual skew control features. The configuration of each device is held in on-chip non-volatile memory that is reprogrammable through a JTAG interface. Certain aspects of the device can be modified on the fly via an I2C interface. Design for the devices is supported in the Lattice PAC- Designer® software tool.

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Lattice Introduces MachXO Mini Development Kit, Reference Designs

Ken Cheung — Mon, 23 Feb 2009 16:40:18 +0000

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the immediate availability of fifteen new reference designs and a new $59 development kit referred to as the MachXOTM Mini Development Kit, which are ideal for prototyping high volume, cost sensitive low density applications. The instant-on, easy to use MachXO programmable logic device (PLD) family offers users the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single device. Designed for a broad range of low density applications that include general purpose I/O expansion, control, bus bridging and power-up management functions, the popular MachXO PLD family is used in a variety of end markets such as consumer, automotive, communications, computing, industrial and medical. In fact, shipments of the MachXO PLD family recently surpassed 15 million units in just over three years.

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Lattice Semiconductor Announces 65nm LatticeECP3 FPGA Family

Ken Cheung — Mon, 23 Feb 2009 16:30:15 +0000

Lattice Semiconductor Corporation (NASDAQ: LSCC) announced its third generation high value FPGAs, the mid-range 65nm LatticeECP3[tm] family, which offers the industry’s lowest power consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu’s advanced low power process technology, and is the only 65nm mid-range, high value FPGA family in the industry.

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