Hella Aglaia Selects Impulse C to FPGA Xilinx FPGAs for 3D Passenger
Impulse Accelerated Technologies announced that Hella Aglaia has completed a design for a Hella Aglaia computer vision 3D automatic passenger counting system using Impulse C to FPGA tools and Xilinx FPGAs in an ASIC prototyping flow. Based on 3D-Sense Technology Hella Aglaia’s self contained Automatic Passenger Counting System AVC 1 offers a counting accuracy greater than 98%. It is possible to verify all results at any time, through the comparison with video recordings.
Xilinx Debuts 6 New Virtex-6 FPGA and Spartan-6 FPGA Development Kits
Xilinx, Inc. (Nasdaq: XLNX) announced six new development kits as part of its Targeted Design Platforms for enabling developers to focus on innovation and differentiation when designing with FPGAs. These development platforms for the Virtex®-6 and Spartan®-6 families significantly shorten the time it takes to reach optimal levels of system performance, while ensuring low levels of power consumption during system-on-chip (SoC) development. The new kits target embedded processing, DSP and the building of systems that require high-speed serial connectivity by providing design teams with optimized tool suites tuned to their design flow, fully functional IP, and Targeted Reference Designs common to their areas of expertise.
Vanguard Software Solutions Becomes Member of Xilinx Alliance Program
Vanguard Software Solutions, Inc. (VSOFTS), a recognized leader in development of video coding products and technologies, has joined the Xilinx Alliance Program as a supplier of AVC Encoder IP Core solutions. As of the date of this press release, VSOFTS has made available its highly flexible AVC-Intra Encoders and CABAC Encoder/Decoder IP Cores for Xilinx® Virtex® FPGA and Spartan® FPGA-based solutions to Xilinx FPGA customers. These IP Cores are optimized for the Virtex architecture, and designed to provide the highest level Broadcast quality compression in a compact, low power design.
Xilinx Simplifies Power Design with TI Digital Power Management
Texas Instruments (TI) (NYSE: TXN) announced Xilinx is using TI power management technology to simplify power design in its new Virtex(R)-6 ML605 field programmable gate array (FPGA) evaluation kit. TI’s Fusion Digital Power(TM) controllers give FPGA users advanced power management capability and design flexibility, including the ability to monitor a power system’s behavior in real time.
EDA/SOPC Lab Opens at Peking University School of Software and Microelectronics
Altera Corporation (NASDAQ:ALTR) announced the opening of the new Peking University and Altera International Limited Joint EDA/SOPC Lab at the Peking University School of Software and Microelectronics (Wuxi), Jiangsu Province, China. This is the 66th Joint Lab and Training Center (JLTC) that Altera has established with major universities in China. As part of Altera’s worldwide University Program, the JLTCs are equipped with the latest Altera® Quartus® II design software and a set of Altera DE2-70 development kits to aid professors in conducting hands-on training with students.
Xilinx Virtex-5 FPGA Powers Vulcan SP HT6210 Network Interface Card
Commex Technologies Ltd., a provider of intelligent, high-performance data-routing solutions for x86 multicore systems, revealed that its Vulcan SP HT6210 Network Interface Card (NIC) has achieved data throughput of 27 Gbps. The Commex NIC accomplishes this unparalleled bandwidth by maximizing the performance of its onboard Xilinx® Virtex®-5 FPGA, and by leveraging the board’s 16-lane, 1.2Gtps HyperTransport bus interface.
Icera Espresso 300 3G Soft Modem Features QuickLogic ArcticLink CSSP
QuickLogic Corporation (NASDAQ: QUIK), the lowest power programmable solutions leader, announced the selection of its Customer Specific Standard Product (CSSP), based on the ArcticLink solution platform, for the Icera Espresso® 300 3G soft modem platform, that is now entering production. Icera is a leader in software-defined wireless chipsets and is the only company to deliver software-based cellular modems for broadband data cards, USB sticks, and mobile internet devices. Icera’s reference design uses a wafer-level chip scale (WLCSP) version of the ArcticLink solution platform to compliment its second-generation baseband chip design. QuickLogic provides higher speed, smart data transfers between USB and SD/SDHC memory via QuickLogic’s innovative Smart Programmable Integrated Data Aggregator (SPIDA) system block.
Cadence, Xilinx Team on Verification for FPGA Targeted Design Platforms
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it has teamed with Xilinx to enable delivery of encrypted simulation models of Xilinx intellectual property (IP) in the latest 11.2 release of the Xilinx ISE Design Suite. The result is an expanded library of design IP and complementary simulation models supported by the Cadence® Incisive® functional verification platform for the new Xilinx Base Targeted Design Platform. Used in conjunction with the Open Verification Methodology (OVM) to provide multi-language verification and reuse, this approach can help mutual customers reduce risk and boost schedule predictability and quality.
Actel Cup China Students FPGA Design Competition Winners
Actel Corporation (Nasdaq: ACTL), the leader in low-power and mixed-signal FPGAs, announced the winners of its 2009 Actel Cup China Students FPGA design competition. Chosen from more than 300 submissions by students from 190 universities, designs from Xian University of Electronic Science and Technology and South China Agricultural University were tied for first place, meeting the contest’s very high standards for creativity, including three key qualifications: high level of innovation, immediate market viability and easy system implementation. This year’s competition was co-sponsored with Guangzhou ZLGMCU Development Company (ZLGMC).
Achronix Announces Encryption Standard IP Cores for Speedster
Achronix Semiconductor, maker of the world’s fastest field-programmable gate arrays (FPGAs), announced the availability of new, high-performance Advanced Encryption Standard (AES) IP cores for its Speedster[TM] 1.5 GHz family. These high-performance 128-bit key size AES cores, from Portland, Ore.-based Signali Corp., are targeted at 10 Gbps, 40 Gbps, and 100 Gbps applications. They demonstrate the speed of the Speedster FGPA fabric, as well as the balance between throughput performance and resource minimization achieved by the Signali Cores.
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