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'Foundry' Category Archive

Intel’s and Micro’s 20nm Multi-level Cell NAND Flash Memory

Posted by Ken Cheung in Components,Foundry on Friday, April 15, 2011

IM Flash Technologies (IMFT) will manufacture a new 20nm 8-gigabyte multi-level cell (MLC) NAND flash device. IMFT is a NAND flash joint venture of Intel and Micron Technology. The 20-nanometer 8GB device is sampling now. It will enter mass production in the second half of this year. Also later this year, Intel and Micron will start sampling a 16GB device. As a result, up to 128GBs of capacity can be packed into a single solid-state storage solution that will be smaller than a U.S. postage stamp.

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X-FAB Silicon Foundries Announces Ready-to-Use Hall Sensor

Posted by Ken Cheung in Foundry on Tuesday, November 30, 2010

X-FAB Silicon Foundries, the leading analog/mixed-signal foundry and expert in “More than Moore” technologies, became the first pure-play foundry to deliver integrated Hall effect functionality as a fully characterized, documented and ready-to-use Hall sensor device. Implemented in X-FAB’s 0.18 micrometer high-voltage process technology (XH018), the new low-power, highly sensitive magnetic field sensor device is a perfect fit for battery-powered applications. It allows engineers to change the system architecture of the entire sensing application into a more cost-effective single-chip solution that requires no further layout work, additional chip testing, measurements or optimization. X-FAB also is delivering a design kit add-on that provides everything designers need to successfully integrate this device with the rest of the circuitry on the chip.

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International SEMATECH Announced Mature Fabs Program

Posted by Ken Cheung in Foundry on Thursday, November 4, 2010

To improve manufacturing productivity, cost and cycle time for a targeted segment of manufacturers in the semiconductor industry, International SEMATECH Manufacturing Initiative (ISMI), announced that it has launched a new Mature Fabs program. ISMI’s Mature Fabs program will be dedicated to addressing the challenges faced by semiconductor companies with mature fabs, including cost and productivity pressures, equipment lifecycle management, safety procedures, and logistics. As a part of the new program, members will share key strategies to address common equipment and factory processing issues.

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Atrenta, TSMC Team on Synthesizable IP for SpyGlass Platform

Posted by Ken Cheung in Design Flow,Foundry on Thursday, October 21, 2010

Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, disclosed details of a collaboration with TSMC to enhance the quality of delivered synthesizable IP using Atrenta’s SpyGlass® platform. SpyGlass is Atrenta’s register transfer level (RTL) analysis and optimization product suite that analyzes and optimizes the quality of integrated circuit designs early in the design process, before expensive and time-consuming physical implementation begins.

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Intel to Invest up to $8 Billion on American Manufacturing Facilities

Posted by Ken Cheung in Foundry on Tuesday, October 19, 2010

Intel Corporation announced that the company will invest between $6 billion and $8 billion on future generations of manufacturing technology in its American facilities. The action will fund deployment of Intel’s next-generation 22- nanometer (nm) manufacturing process across several existing U.S. factories, along with construction of a new development fabrication plant (commonly called a “fab”) in Oregon. The projects will support 6,000 to 8,000 construction jobs and result in 800 to 1,000 new permanent high-tech jobs.

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Mentor Graphics Supports Open Process Design Kit Coalition

Posted by Ken Cheung in EDA Tools,Foundry on Friday, October 15, 2010

Mentor Graphics Corporation (NASDAQ: MENT) reinforced its support for the work of the Open PDK (Process Design Kit) Coalition with the announcement that Linda Fosler, director of marketing for the Deep Submicron Division, will serve as Open PDK Coalition Vice-Chair. The goal of the Open PDK Coalition is to define a set of open standards to allow a PDK to be as portable across foundries and as agnostic to EDA tools as possible.

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Mentor Graphics, GLOBALFOUNDRIES Publish Graphical Design Rule Manual

Posted by Ken Cheung in EDA Tools,Foundry on Thursday, August 26, 2010

Mentor Graphics Corporation (NASDAQ: MENT) announced it has collaborated with GLOBALFOUNDRIES to create a facility called Graphical Design Rule Manual (GDRM) that helps IC designers rapidly debug layout design rule violations by integrating the Calibre® RVE[TM] results viewing environment with GLOBALFOUNDRIES’ electronic design rule manuals. With GDRM, designers using the Calibre RVE tool to correct DRC hotspots can automatically access detailed GLOBALFOUNDRIES textual and graphical reference information about the specific rules generating the violations. By providing instant access to relevant information, the solution allows designers to fix errors more quickly and reduce time to signoff.

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GLOBALFOUNDRIES, Synopsys Team on DesignWare Interface PHY IP for 28nm

Posted by Ken Cheung in Foundry,IP Cores on Wednesday, August 4, 2010

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, and GLOBALFOUNDRIES, a leading provider of advanced semiconductor technology and manufacturing services, announced an agreement to develop the Synopsys DesignWare® SuperSpeed USB (3.0), USB 2.0, HDMI 1.4 Tx and Rx, DDR3/2, PCI Express® 2.0 and 1.1, SATA 1.5/3 Gbps and 6 Gbps, and XAUI PHY IP for GLOBALFOUNDRIES’ 28-nanometer (nm) “Gate First” High-k Metal Gate (HKMG) process technologies. The collaboration will enable mutual customers to differentiate their 28nm designs with a high-quality IP portfolio targeted at next-generation electronic system-on-chips (SoCs). The long-standing relationship between the two companies has resulted in the successful development of DesignWare PHY IP from 180-nm to 32-nm process technologies. GLOBALFOUNDRIES and Synopsys are the first to announce the development of USB, PCI Express, DDR, HDMI, SATA and XAUI PHY IP targeting 28-nm process technologies with scalability to future generations.

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SMIC Moves Low Leakage 65 Nanometer Technology to Volume Production

Posted by Ken Cheung in Foundry on Tuesday, August 3, 2010

Semiconductor Manufacturing International Corporation (“SMIC”, NYSE: SMI and HKSE: 981), a world leading semiconductor foundry and the most advanced in Mainland China, announced that its Low Leakage 65-nanometer (nm) technology, implemented at SMIC’s 300mm facility in Beijing, has successfully moved to Volume Production Stage. The 65nm accumulative wafer shipment has achieved over 10,000 pieces since its mass production began in Q3 2009.

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X-FAB Develops 100V High Voltage 0.35 Micrometer Foundry Process

Posted by Ken Cheung in Foundry on Thursday, July 15, 2010

X-FAB Silicon Foundries, the leading analog/mixed-signal foundry and expert in “More than Moore” technologies, announced the industry’s first 100V high-voltage 0.35 micrometer foundry process. It enables a new class of reliable, high-performing battery monitoring and protection systems for lithium ion battery management. It also is ideal for power management applications and for ultrasonic imaging and inkjet print head apps using piezoelectric drivers. In addition, X-FAB added new and enhanced N- and P-type double-diffused metal-oxide-semiconductor (DMOS) transistors with 45 percent lower on-resistance for multiple operating voltages up to 100V, lowering the silicon footprint by up to 40 percent and thus reducing die costs. X-FAB will thoroughly discuss these new capabilities in a free webinar, “Addressing High-Voltage Applications with the Industry’s First 0.35 Micrometer 100V Pure-Play Foundry Process,” offered worldwide on July 27 and 28.

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