Innovative Silicon to Highlight Embedded Floating Body Memory Macro
Innovative Silicon, Inc. (ISi), developer of the Z-RAM® zero-capacitor floating body memory technology, announced the upcoming delivery of a presentation titled “A 2ns-Read-Latency 4MB Embedded Floating Body Memory Macro in 45nm SOI Technology” in collaboration with AMD at the International Solid State Circuits Conference (ISSCC). The findings, highlighted in a co-authored paper, result from collaborative efforts between the two companies over the past three years to bring-up Z-RAM memory on a contemporary SOI process technology. Unlike ISi’s focus on developing Z-RAM memory as a stand-alone DRAM replacement, this paper will demonstrate Z-RAM memory implemented as an ultra-dense, multi-megabit, on-chip cache memory which occupies approximately 60 percent less area than conventional cache memories. The presented results demonstrate the fastest floating-body memory array reported, and the most advanced technology node reported.
IP 09 Combines with Embedded Systems Conference
IP/SoC 09 (IP-Based System Design) will be the 18th edition of the working conference on hot topics in the SoC design world. Held each held each year in the well known Silicon and Nanometer Valley in the French Alps, IP 09 will combine this year with Embedded Systems Conference to provide a unique, integrated IP-to-System event in Grenoble, December 1-3, 2009.
Certeon Offers Webinar on IBM Rational ClearCase, Team Concert
Certeon, the industry’s first and only vendor to offer a virtualized appliance for application acceleration, announced that it will be hosting a Webinar on improving the performance of distributed IBM Rational ClearCase and Team Concert environments. Charlie Kraus, senior director of business development for Certeon, and Paul Weiss, senior manager of performance and reliability, Rational Division IBM Software Group, will discuss how Certeon’s aCelera application acceleration software cost-effectively reduces Rational ClearCase and Team Concert application response times over the WAN by as much as 93%.
DesignCon Sessions Feature Apache Design Solutions
Apache Design Solutions, the technology leader in power and noise integrity for chip, package, and system convergence, announced that they will be participating in several technical and business conference sessions at the upcoming DesignCon Conference held in Santa Clara, California. Apache’s key executives will be discussing the latest challenges and solutions in maintaining power, noise, and thermal integrity and driving convergence across IC, package, system, and SiP designers.
Agilent to Showcase Jammer, Jitter Tolerance Test, Channel Simulator
Agilent Technologies Inc. (NYSE: A) at DesignCon will demonstrate the industry’s first PCI Express Jammer, a jitter-tolerance test for embedded and forwarded clock devices, a million-bit-per-minute channel simulator, and a new powerful signal integrity toolset. Also on display include solutions for high-performance probing, high-speed interconnect analysis/simulation, FPGA debug for front-side CPU buses, FBD/DDR memory, Serial-ATA, USB, HDMI 1.3, DisplayPort, 10 Gigabit Ethernet and Fibre Channel.
Altera to Present, Demonstrate Stratix IV GX / GT FPGAs at DesignCon
Altera’s newly announced 40nm Stratix IV GT, the industry’s only FPGAs with integrated 11.3Gbps transceivers optimized for 40G/100G applications, and Stratix IV GX FPGAs operating at 8.5Gbps will be demonstrated on the Stratix IV signal integrity board at the Tektronix booth #405 and Agilent Technologies booth #305, February 4-5, at the Santa Clara Convention Center.
MatrikonOPC Announces eLearning Program for Automation Professionals
MatrikonOPCTM is proud to announce the release of a new eLearning program that offers automation professionals a convenient way to learn about OPC. Learning OPC has never been easier, or more economical. The first available module, “Introduction to OPC”, introduces students to the basics of OPC including the most common version, OPC Data Access. Using a combination of interactive PowerPoint slides with voice-overs, demonstrative videos, and knowledge affirming quizzes; this module engages students on multiple levels. MatrikonOPC eLearning requires no travel and no time away from the workplace.
Apache Design Solutions to Take Part in DesignCon Sessions
Apache Design Solutions, the technology leader in power and noise integrity for chip, package, and system convergence, announced that they will be participating in several technical and business conference sessions at the upcoming DesignCon Conference held in Santa Clara, California. Apache’s key executives will be discussing the latest challenges and solutions in maintaining power, noise, and thermal integrity and driving convergence across IC, package, system, and SiP designers.
International Engineering Consortium Announces DesignCon IP Summit
The International Engineering Consortium’s (IEC) introduces the new IP Summit, a featured program fully integrated with the DesignCon conference and exhibition February 2-5 at the Santa Clara Convention Center. The IP Summit will address the role of semiconductor IP in electronic design through featured speakers, panels, tutorials, technical papers and exhibits.
Virtutech to Take Part in DesignCon Multicore, Virtualization Panels
Virtutech, Inc. the leading provider of virtualized system development (VSD) solutions, announced that its principal technology specialist Ross Dickson will take part in panel discussions at DesignCon at the Santa Clara Conventions Center in Santa Clara, CA: “Multicore and Virtualization Key Enablers for Next-Generation Network Architecture,” from 1:30 to 4:30 PM PT, on Monday, February 2, at DesignCon 2009, and “Power Architecture Ecosystem Solution Offerings,” from 10:45 a.m. – 11:00 AM PDT, on Thursday, February 5.
« Newer Posts || Older Posts »
If you are familiar with RSS feeds, you can also sign up for our free news feed. Our RSS feed is updated in real-time while our newsletter is updated daily.