Embedded Masterclass Workshop Features Embedded Linux Workshop
Embedded Masterclass 2009 is to include an Embedded Linux workshop and will be held in Cambridge and Bristol on the 7th and 12th May. The UK conference and exhibition for hi-tech developers, The Embedded Masterclass, will include a workshop to introduce developers to the Linux operating systems for use in embedded systems. This is a re-run of last year ’s workshop that 57 engineers attended and that was oversubscribed. This workshop shows how to build a working embedded Linux system, using an ARM development board as the target. Topics covered include cross-development tools, kernel configuration and compilation and the essential components of a root file system. The combination of theory and practice will give delegates an insight into the working of Linux in embedded environments. The workshop is 50% practical and 50% theory.
Embedded Alley Announces Smart Design Webinars for Developers
Embedded Alley, a leading provider of embedded Linux® solutions, announced the first in a series of “Smart Design” on-line seminars to help developers tackle tough challenges in building intelligent devices with Linux. The debut is slated for February 17, 2009; together with Freescale Semiconductor, Embedded Alley will present “Smart Storage Choices for Intelligent Devices.” The joint webinar will target software/hardware integration and optimization of embedded Linux, Freescale i.MX-family application processors, and flash memory storage.
Atmel, Adeneo Embedded Offer Windows CE 6.0 R2 Training for AT91SAM ARM9
Atmel® Corporation (Nasdaq: ATML) and Adeneo Embedded announced a Microsoft® Windows® Embedded CE 6.0 R2 training course in Paris, France from February 23 to 26, 2009. This event is a unique opportunity for software system designers to develop an application based on Windows Embedded CE, and on the industry leading AT91SAM9. The AT91SAM9 is an Embedded MPU based on the ARM926EJ-SÔ core which is rapidly becoming a platform of choice for embedded designers.
Geensys to Launch at ASIM Simulation Module, Reqtify 2009
Geensys (Hall 10, Stand 214) will make several announcements relating to its highly successful AUTOSAR Builder, ControlBuild and Reqtify embedded software development tools. At Embedded World, Geensys will launch the ASIM simulation module for its AUTOSAR Builder tool suite facilitating the validation and verification of AUTOSAR systems early in the development cycle. ASIM will initially provide VFB-Level simulation to test Software Component sets without any hardware constraints and ECU-level simulation taking into account the addition of PC-based BSW implementation and configuration. ASIM will subsequently provide Network-level simulation, processing the artefacts of the entire system topology including network data.
ISQED Asia Symposium on Quality Electronic Design
The International Society for Quality Electronic Design (ISQED.org) announced the “1st Asia Symposium on Quality Electronic Design” (ISQED-ASIA’09). This event which will take place on July 15-16 of 2009 in KL Malaysia, is the first event organized by ISQED organization in continental Asia. ISQED-ASIA’09 will span two days, Wednesday and Thursday, in three parallel tracks, hosting over 60 technical presentations; several keynote speakers, tutorials and other informal meetings. Conference proceedings are planned to be published by IEEE and posted in the digital library.
SDR Forum Issues Call for Papers
The SDR Forum, a non-profit international industry association dedicated to promoting the success of next generation radio technology, has announced it is accepting abstracts and proposals for its annual technical conference and product exposition, SDR’09. SDR’09 will be held 1-4 December 2009, in Washington, D.C. Last year’s event, also held in Washington, D.C., attracted more than 400 attendees from 27 countries, representing all aspects of the reconfigurable radio value chain, from research through deployment. This year, SDR’09 will feature more than 40 exhibitors, as well as four full days of presentations, workshops and tutorials/demonstrations.
System-on-Chip Conference Issues Call for Speakers
Savant Company Inc. announced a call for sponsors and speaker presentations for the 7th International System-on-Chip (SoC) Conference, which will be held at the Radisson Hotel Newport Beach, California, on Wednesday, November 4th, and Thursday, November 5th, 2009. For speaking opportunities at the SoC Conference, for Tabletop Exhibit information, and to develop highly targeted Workshops, please contact the SoC Conference Organizing Committee at: SoC@SavantCompany.com.
Live EDGE Electronic Design for Global Environment Competition
Premier Farnell plc (LSE:pfl), the leading multi-channel, high service distributor and its companies (Farnell, Newark, Premier Electronics, Farnell-Newark CPC, and MCM), announced that design submissions for the international design competition, Live EDGE – Electronic Design for the Global Environment will close on the 31st of January 2009. Since the competition’s launch in October 2008, design engineers, students and academics from around the world have registered to submit designs for an innovative product that utilises electronic components and has a positive impact on the environment. The majority of registrations to date have come from India, the US and China.
Synfora Enhances PICO Extreme Algorithmic Synthesis Design Tools
At the Electronic Design and Solution Fair 2009 (EDSFair2009) in Yokohama, Japan, the week of January 19, 2009, Synfora, Inc., will announce and demonstrate the capabilities of enhanced versions of its PICO Extreme[tm] and PICO Extreme FPGA algorithmic synthesis design tools. Enhancements will include QoR (Quality of Results) improvements in terms of area, timing and timing correlation, reporting and feedback enhancements, and improved code coverage for PICO RTL (Register Transfer Language).
Atrenta Announces Design Closure Stimulus Package Seminars
Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, announced a worldwide Design Closure Stimulus Package seminar series. These seminars will assist chip companies to build better products, both faster and more economically, by detecting and mitigating design risks earlier in the design process than ever before.
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