Synopsys Acquires CoWare
CoWare®, Inc., a leading supplier of Electronic System Design software and services, announced that it has signed a definitive agreement to be acquired by Synopsys, Inc. (Nasdaq: SNPS), an industry leader in software and IP for semiconductor design, verification and manufacturing. CoWare brings to Synopsys a range of electronic system design solutions covering processor design, system architecture design, verification, software development, and algorithm design.
APAC IC Layout Consultant Selects Synopsys Galaxy Custom Designer
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that APAC IC Layout Consultant, Inc., a global provider of IC physical design services, has adopted Synopsys’ Galaxy Custom Designer[tm] implementation solution. APAC IC, based in the Philippines, benefited from the ease with which Galaxy Custom Designer can be adopted to quickly achieve high productivity for its team of layout engineers servicing a worldwide customer base. APAC IC selected Galaxy Customer Designer because of its productive and streamlined design environment and its openness for interoperability. APAC IC’s custom design flow also includes Synopsys’ HSPICE® circuit simulation, CustomSim[tm] FastSPICE simulator, Hercules[tm] physical verification and StarRC[tm] parasitic extraction solutions.
Apple iPad to Drive Tablet PC Semiconductor
The debut of the iPad promises significant opportunities well beyond just Apple. The iPad promises to energize the emerging tablet PC segment, creating a potential semiconductor opportunity of over US$4.1 billion in 2014, reports In-Stat. Other component vendors will capitalize on the new opportunity for batteries and displays, as well.
ASIA Company Deploys Mentor Graphics CHS Tools for Wire Harness Design
Mentor Graphics Corporation (NASDAQ: MENT) announced that ASIA Company, a Korea-based wire harness supplier, has made dramatic gains by deploying the CHS[TM] software. The CHS tool has enabled ASIA to add significant automation and cut their wire harness design cycle time by up to 75 percent. ASIA supplies GM-Daewoo, which in turn uses standardized General Motors design tools and methodology.
Microchip Technology Acquires Silicon Storage Technology
Microchip Technology Incorporated (NASDAQ:MCHP), a leading provider of microcontrollers and analog semiconductors, announced that it has signed a definitive agreement to acquire Silicon Storage Technology, Inc. (Nasdaq:SSTI) for $2.85 per share in cash. The $2.85 per share represents an approximate 35.7% premium to the amount that the holders of SST common stock would have received under the previously announced merger agreement between SST and Technology Resources Holdings, Inc., and an approximate 53.2% premium to the closing price per share of SST’s stock on November 12, 2009, the last day of trading prior to the announcement of the execution of the definitive merger agreement with Technology Resources Holdings, Inc. As separately announced by SST, SST has terminated its previously announced merger agreement prior to entering into the definitive agreement with Microchip.
Aeroflex Deploys Synopsys CustomSim Unified Circuit Simulation Solution
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Aeroflex Colorado Springs, Inc., a global provider of high-technology solutions to the aerospace, defense and broadband communications markets, has successfully deployed Synopsys’ CustomSim[tm] unified circuit simulation solution for the development and verification of its high-reliability integrated circuits (ICs). The CustomSim solution delivers performance improvements of up to 60x over SPICE, increasing designer productivity and confidence by enabling more corners to be run for transistor-level verification of large blocks. In addition, taking advantage of the Discovery[tm] Verification Platform by using the CustomSim solution with Synopsys’ VCS® functional verification solution enables full-chip, mixed-signal simulations that were not possible with previous-generation simulators, allowing Aeroflex to reduce design cycle times.
austriamicrosystems Broadens Deployment of Cadence EDA Tools
Cadence Design Systems Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that austriamicrosystems (SIX: AMS), a leading global designer and manufacturer of high-performance analog ICs for communications, industrial, medical and automotive applications and foundry services, has broadened its deployment of Cadence® technology. Over the last two decades, austriamicrosystems has relied on the Cadence Virtuoso® custom IC design platform for its analog and mixed-signal designs and process design kits (PDKs). By choosing Cadence® Encounter® Digital Implementation System for the digital part of its designs, the company can now ensure a tight integration between its design flows.
Cadence Leverages STARC Regression Suites for Chip Design
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, and Semiconductor Technology and Academic Research Center (STARC), the Japan semiconductor industry consortium, revealed an ongoing collaboration to leverage STARC’s regression suites to ensure the high quality of electronic design automation (EDA) software for advanced chip design. The regression suites and validation flow were developed by STARC and its member companies to qualify EDA software for use by consortium members.
Toshiba Standardizes on Verification Methodology Manual for Low Power
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced that Toshiba Information Systems (Japan) has standardized on the Verification Methodology Manual for Low Power (VMM-LP) to verify its low power chip designs. Incorporating industry best practices from the collective real-life experiences of more than 30 companies, the VMM-LP provides a framework for accelerating the verification of low power designs. Toshiba Information Systems (Japan) used Synopsys’ voltage-aware VCS® functional verification solution with MVSIM and VMM-LP to deploy a uniform, structured and repeatable verification methodology across its low power design projects.
NEC Selects Cadence Encounter Digital Implementation System
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, and NEC Electronics Corporation (TSE: 6723), a leading provider of semiconductor solutions, announced that NEC Electronics has adopted Cadence® Encounter® Digital Implementation (EDI) System and succeeded in more than ten complex ASIC designs targeting its CB40L (40 nanometer low power) process technology with several designs successfully taped out already. Utilizing more than 20 million gates, the scale of the new ASICs has increased by two- to four-times over previous designs targeting 55-nanometer (nm) and 90-nm process technologies. EDI Systems’ multi-threaded processing, netlist-to-netlist compilation, and integrated DFM optimization and timing signoff analysis, streamlined the large ASIC design processes.
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