'EDA Tools' Category Archive

Digi TransPort VPN VC7400 Connects Remote Wireless Devices

Posted by EDA Geek News Staff in EDA Tools on Tuesday, June 30, 2009

Digi International (NASDAQ: DGII) introduced the Digi TransPort VC7400, an enterprise-class virtual private network (VPN) concentrator that provides easy, secure connectivity to large installations of remote cellular or wired devices. It is ideal for retail, financial/ATM, lottery and telemetry applications. Coupled with Digi’s VPN enabled cellular routers at remote sites, the centralized Digi TransPort VC7400 makes it easy to set up a secure, reliable and fully integrated VPN solution.

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SPIRIT Consortium Hands Off IP-XACT v1.5 Specification to IEEE P1685

Posted by EDA Geek News Staff in EDA Tools on Monday, June 29, 2009

The SPIRIT Consortium[tm], a global non-profit organization focused on establishing multi-faceted IP/tool integration standards that drive sustainable growth in electronic design, has approved version 1.5 of its IP-XACT[tm] specification for handoff to the IEEE P1685 working group. The IP-XACT specification provides a machine readable XML structure for IP modules and systems databooks. The XML data documents many different aspects of electronic design elements, enabling designers using IP-XACT tools to automatically create many different expressions of a design in a consistent and correlated way. Design and verification engineers will benefit from using this available specification through the automation testbench creation and exploration.

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Cadence, Toshiba Team on Integrated Design Environment for COT, SoC

Posted by EDA Geek News Staff in EDA Tools on Monday, June 29, 2009

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced an extensive collaboration with Toshiba Corporation Semiconductor Company to address the challenges of existing and next-generation SoC designs. Toshiba is a leading provider of process and design solution for cutting-edge SoC products. Based on the Cadence® Encounter® Digital Implementation System and the Cadence Virtuoso® Custom Design Solution, the collaboration provides a full digital and mixed-signal design environment to Toshiba and its COT customers for the most advanced semiconductor products where integration of digital and mixed-signal designs is a key to success.

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Zocalo Tech Rolls Out Zazz EDA Software

Posted by EDA Geek News Staff in EDA Tools on Thursday, June 25, 2009

Zocalo Tech, Inc., an Electronic Design Automation (EDA) company focusing on Assertion Based Verification (ABV) productivity software, is shipping Zazz[tm] . Zazz, first introduced at DVCon in February 2009, is the first EDA software product to make using assertion libraries quick, easy and accurate by automating tedious error prone tasks with its easy to use intuitive Graphical User Interface (GUI). With Zazz, the checkers from the most widely used assertion libraries can be attached to a design and documented in minutes.

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Cadence, Xilinx Team on Verification for FPGA Targeted Design Platforms

Posted by EDA Geek News Staff in EDA Tools, FPGAs on Wednesday, June 24, 2009

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced that it has teamed with Xilinx to enable delivery of encrypted simulation models of Xilinx intellectual property (IP) in the latest 11.2 release of the Xilinx ISE Design Suite. The result is an expanded library of design IP and complementary simulation models supported by the Cadence® Incisive® functional verification platform for the new Xilinx Base Targeted Design Platform. Used in conjunction with the Open Verification Methodology (OVM) to provide multi-language verification and reuse, this approach can help mutual customers reduce risk and boost schedule predictability and quality.

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Synopsys, TSMC Team on 28nm Lithography Verification

Posted by EDA Geek News Staff in EDA Tools, Foundry on Tuesday, June 23, 2009

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, announced the results of a collaboration with TSMC under TSMC’s Unified Design-for-Manufacturing (UDFM) architecture effort. This collaboration enables designers to improve yields and accelerate time to market through more accurate lithography simulation at 28 nanometer (nm) and below. Through this joint effort, designers will now have access to the same technology that is in production at TSMC. The solution offers a 28-nm lithography process checking (LPC) engine, which includes Synopsys Proteus mask synthesis technology and TSMC process models. Using an interoperable applications programming interface (API), EDA design tools can now interface with the LPC engine to accurately predict lithography hotspots in a given design before handing-off the designs to manufacturing.

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