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'Design Services' Category Archive

Ampro ADLINK Technology Forms Design Partner Network

Posted by Ken Cheung in Design Services on Tuesday, March 24, 2009

Ampro ADLINK Technology, Inc., a global provider of trusted embedded products, announced the formation of its Design Partner Network—a growing network of well-known electronic engineering design services firms. The intent of the network is to ensure that Ampro ADLINK’s prospects and customers have immediate access to professional and technical engineering design services, either internally with Ampro ADLINK or via one of the partners, for the design and development of custom carrier boards for ETX and COM Express embedded systems solutions and applications.

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Pebble Bay Announces Embedded Software Optimisation

Posted by Ken Cheung in Design Services on Thursday, March 19, 2009

Pebble Bay, the independent experts in diagnosing and solving business limiting embedded software problems, launches an initiative in response to OEMs affected by present economic conditions. The new service is called Embedded Software Optimisation (ESO), and can enable OEMs to significantly improve their existing products at costs that are an order of magnitude less than developing new products – saving hundreds of thousands or even millions of pounds in NRE (Non-Recurring Engineering) costs.

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Nangate Announces Standard Cell Library Development Services

Posted by Ken Cheung in Design Services on Thursday, February 26, 2009

Nangate, the leading provider of tools for application-specific digital cell library development, announced that it is offering library development services to assist customers in the development of standard-cell libraries for a wide range of CMOS process technologies, from mature nodes to leading-edge 32nm and 28nm processes.

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Synopsys Announces DesignWare DDR PHY Signal Integrity Service

Posted by Ken Cheung in Design Services on Wednesday, February 25, 2009

Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, announced a service that delivers a customized signal integrity report to help designers verify their DDR3/2 timing budgets and printed circuit board environments. As DDR SDRAMs operate at faster speeds, the effects induced by the high data rate can degrade the electrical signal to the point where errors result and the receiver does not interpret the data properly. The DesignWare® DDR PHY signal integrity service examines the entire memory subsystem extending far beyond the DDR PHY to help ensure the robustness of the electrical signaling within the system. If necessary, the service offers recommendations for improved performance.

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Jasper Design Automation Announces Design Activation Services

Posted by Ken Cheung in Design Services on Monday, February 23, 2009

Jasper Design Automation, provider of advanced formal technology solutions, announced its Design Activation Services to help both design houses and commercial IP vendors reap the benefits of design and IP reuse, amortizing research and development costs over multiple IC design projects. Jasper’s new service offering consists of specialized consulting to deliver an Activated Design – an executable design database – for a particular design block, several blocks, or an entire library. Design Activation Services promote easy comprehension, delivery and efficient reuse of both legacy designs and commercial IP. Design Activation Services leverage the company’s recently announced ActiveDesign[tm] with Behavioral Indexing[tm], along with the expertise of its formal applications team. Jasper’s Design Activation Services and Activated Designs target SoC designers who use internal IP, commercial IP providers that want to proliferate their IP, and design services companies supporting platform-based designs.

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Sarnoff Europe Announces Low Threshold Consulting, Testing Services

Posted by Ken Cheung in Design Services on Tuesday, December 2, 2008

Sarnoff Europe announced complementary low threshold consulting and testing services to its TakeCharge® silicon IP-based Electrostatic Discharge (ESD) portfolio licensing. The new consulting service leverages Sarnoff Europe’s experience in providing silicon and product proven ESD solutions over 8 consecutive CMOS generations (0.5um down to 40nm) in multiple foundries. A team of 14 engineers uses advanced, proprietary tools to achieve quick turnaround for customer ESD risk assessment, design and layout review, debugging, ESD rules and guidelines, GDSII cells, IO/IC integration, calculation, and optimization.

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Marklin Digital Selects Kontron for Central Station 60213

Posted by Ken Cheung in Design Services on Friday, November 28, 2008

Kontron presented the hardware platform for the new Central Station 60213 from Märklin Digital. With its manifold tailor-made interfaces, the new platform underlines Kontron’s competence in embedded computer technology. The platform, which Märklin introduced in September 2008, offers more application flexibility than any other known control system for model railways. It communicates via Märklin’s own interfaces as well as numerous standard interfaces such as, for example, USB and Ethernet and repesents a new milestone in the control of complex model railways. Enthusiasts with smaller setups will also get the most out of this new control platform.

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Embedded Alley Optimizes Flash Memory Deployment in Intelligent Devices

Posted by Ken Cheung in Design Services on Thursday, November 6, 2008

Embedded Alley, a leading provider of embedded Linux® solutions, announced the introduction of a specialized consulting practice, and accompanying technology and tools to optimize deployment of mobile, consumer electronics and other intelligent systems utilizing flash memory. Flash memory is pervasive in modern intelligent devices, for storage of applications, photographs, multimedia and other content. Available flash technologies, however, can force OEMs to make difficult trade-offs between component costs and device longevity. In particular, NAND flash technology comes in two main varieties: Multi-Level Cell (MLC) and Single Level Cell (SLC). The more popular MLC is less expensive in high capacity configurations, but also presents significantly lower erase-cycle endurance than SLC. MLC can “wear out” after 10,000 block erase/write cycles, and also introduce bit errors from read operations. This combination of both read and write cycle sensitivity presents unique challenges to flash-based designs, leaving OEMs guessing how to choose flash technology and flash-based files systems.

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QNX Creates Automotive Solutions Program for Suppliers, OEMs

Posted by Ken Cheung in Design Services on Wednesday, October 15, 2008

QNX Software Systems, the global leader in operating systems and middleware for the in-car telematics and infotainment market, announced its new QNX Automotive Solutions program for automotive Tier One suppliers and OEMs. The program offers a team of highly experienced QNX engineers who work closely with customer development teams during the planning and design phases to ensure that critical projects start and finish on time and on budget.

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Freescale Semiconductor Unveils Customer Specific Products Business

Posted by Ken Cheung in Design Services on Tuesday, September 30, 2008

To address the market need for highly customized devices, Freescale Semiconductor has launched a Customer Specific Products (CSP) business that provides custom system-on-chip (SoC) solutions based on its industry-leading SoC platforms – Power Architecture® processors, ColdFire® controllers and i.MX platforms based on ARM® technology. Freescale is the only company in the industry to have three distinct processor platforms with proven technologies spanning high performance, low power, multimedia acceleration and embedded control.

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