This combined tool gives designers an end-to-end analog circuit design and simulation environment for creating power supplies to PCB layout.
Guest blog post by Corina Mitu, AMIQ EDA
AMIQ EDA has announced version 3.5 of its flagship solution – DVT Eclipse IDE. The new version provides enhanced compilation, improved UVM support, a streamlined GUI, and simplified deployment to help design and verification engineers increase code development quality and productivity.
The latest EDA Consortium’s Market Statistics Service (MSS) report indicates EDA revenues increased 6.8 percent in Q3 2013 over Q3 2012. CAE and SIP were the big revenue categories both years in the Americas and APAC, but all areas listed in the report showed growth.
The DSMART IP Core combines reduced CPU utilization and small size to handle many smart card reader application tasks. It is based on ISO 7816-3/EMV4.2 requirements with hardware support for T0 character oriented protocol and T1 block oriented protocol.
The complex assembly of many solid objects (such as PCBs, electronics packages and devices, cabling, fans, and heatsinks) inside electronics equipment means air flow is confined within narrow regions between these solid objects. Electronics products pose a unique set of challenges for thermal simulation because of this complexity.
The display interface provides a MIPI DSI bridge from the processor to an embedded DisplayPort LCD at 30 percent higher bandwidth than competing devices. The SN65DSI86 will be demonstrated at the Consumer Electronics Show in 2014.
Cadence Design Systems introduced its Encounter RTL Compiler version 13.1 that can deliver up to 15 percent improvements in power, performance, and area with a new suite of physically aware RTL synthesis capabilities. The production-ready physical synthesis engine enables designers to use physical-aware techniques at earlier synthesis phases for better results in silicon. The new RTL Compiler inserts physical awareness into stages of synthesis that have previously been logic only.
At 28 nm and below, it’s difficult for designers to get optimal timing and closer as interconnect characteristics change. Cadence’s RTL compiler helps these complex and advanced chip designs deal with their timing and congestion challenges, and deal with them sooner. Addressing these problems earlier in the design process helps achieve faster timing closure and improve power, performance, and area.
Encounter RTL Compiler capabilities:
- Physically aware structuring
- Multi-bit cell inferencing
- Design for test
- More than 10 percent performance improvement from physically aware structuring and mapping
- More than 15 percent area improvement on complex SoCs from pin and register placement considerations when choosing which microarchitecture to synthesize to and how to balance them
- 10 percent or more power decrease from physically aware multi-bit cell inferencing by merging single registers into clock-sharing multi-bit registers
Fujitsu Semiconductor collaborated with Cadence and used the new RTL compiler on several production design developments. As a result, they were able to improve timing and area by more than 10 percent, which allowed them to be able to make smaller chips for their customers.
More info: RTL Compiler
Real Intent’s Ascent and Meridian early verification and advanced sign-off solutions will be presented by Director of Strategic Accounts Dr. Roger Hughes at the November 18, 2013 SemIsrael Expo 2013. Dr. Hughes will focus on formal verification’s role in Clock-Domain Crossing (CDC) in the presentation “Formal is Normal: Automatically Refine Your CDC Checking.”