Digital Core Design (DCD) announces new serial bus – the DI2CSB

Digital Core Design (DCD) has released the DI2CSB IP Core, which is a two wire, bidirectional serial bus, and provides an efficient and stable short distance data transmission between multiple devices. The DI2CSB provides an interface between a passive target device (for example: memory, LCD display, pressure sensors, etc.) and an I2C bus. It has a very simple interface, composed with read, write, and data signals, which enables easy connection to a target device.

Member of the Board for DCD, Piotr Kandora, says the DI2CSB can work as a slave receiver or as a transmitter, depending on the working mode determined by the master device. The core is also ready to work after power-up/reset – it does not require any programming. The read, write, burst read, burst write, and repeated start transmissions are automatically recognized by the core.

The DI2CSB is a technology independent design, which is why it can be implemented in a variety of both ASIC and FPGA technologies. The DI2CSB can be easily customized for a variety of project/customer needs. For example, the DI2CSB can be implemented in embedded microprocessor boards, communication systems, cost-effective reliable automotive systems, consumer and professional audio/video, home and automotive radio, and low-power applications.

DI2CSB Features:

  • Conforms to the latest I2C specification
  • Slave operation: Slave transmitter; Slave receiver
  • Supports three transmission speed modes: Standard (up to 100 kbps); Fast (up to 400 kbps); Fast Plus (up to 1 Mbps); High Speed (up to 3-4 Mbps)
  • Allows operation from a wide range of input clock frequencies
  • Support for reads, writes, burst reads, burst writes, and repeated start
  • 7-bit addressing
  • No programming required
  • Simple interface allows easy connection to target device – memory, LCD display, pressure sensors, etc.
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

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