The DSMART IP Core combines reduced CPU utilization and small size to handle many smart card reader application tasks. It is based on ISO 7816-3/EMV4.2 requirements with hardware support for T0 character oriented protocol and T1 block oriented protocol.
- Supports asynchronous smart cards
- Dual configurable length FIFO with 2 programmable thresholds
- Software-configurable imputs
- Automatic convention detection and decoding
- Programmable non-gated card clock generator
- Automatic ETU generator
- Hardware CRC and LCR calculations
- Power down mode holds card clock in stop high or stop low modes
- Optional fast block mode for T1 protocol
Direct memory access (DMA) allows for data transfer to and from the host system. The automatic convention detection and decoding mechanism helps guarantee exact results. The card clock divider provides a non-gated clock with many possible frequencies.
As a configurable IP Core, it can be easily adjusted to the needs of the project. Immediate updates of stored data can allow smart card systems to be used in identification and patient authentication in healthcare, banking wireless payments, and electronic ticketing for transportation applications.
More information: Digital Core Design