Cadence Announces RTL Compiler that Delivers Chip Improvements from Earlier Physically Aware Synthesis

Cadence Announces RTL Compiler that Delivers Chip Improvements from Earlier Physically Aware Synthesis

Cadence Design Systems introduced its Encounter RTL Compiler version 13.1 that can deliver up to 15 percent improvements in power, performance, and area with a new suite of physically aware RTL synthesis capabilities. The production-ready physical synthesis engine enables designers to use physical-aware techniques at earlier synthesis phases for better results in silicon. The new RTL Compiler inserts physical awareness into stages of synthesis that have previously been logic only.

At 28 nm and below, it’s difficult for designers to get optimal timing and closer as interconnect characteristics change. Cadence’s RTL compiler helps these complex and advanced chip designs deal with their timing and congestion challenges, and deal with them sooner. Addressing these problems earlier in the design process helps achieve faster timing closure and improve power, performance, and area.

Encounter RTL Compiler capabilities:

  • Physically aware structuring
  • Mapping
  • Multi-bit cell inferencing
  • Design for test

Improvements include:

  • More than 10 percent performance improvement from physically aware structuring and mapping
  • More than 15 percent area improvement on complex SoCs from pin and register placement considerations when choosing which microarchitecture to synthesize to and how to balance them
  • 10 percent or more power decrease from physically aware multi-bit cell inferencing by merging single registers into clock-sharing multi-bit registers

Fujitsu Semiconductor collaborated with Cadence and used the new RTL compiler on several production design developments. As a result, they were able to improve timing and area by more than 10 percent, which allowed them to be able to make smaller chips for their customers.

More info: RTL Compiler