ASSET InterTech published a new eBook. The publication explains how to test DDR memory with non-intrusive JTAG or boundary-scan (IEEE 1149.1) methods. The title of the paper is Testing DDR3 Memory Boundary Scan JTAG. The paper was written by Kent Zetterberg, product manager, ASSET InterTech.
According to a recent survey of engineers by the International Electronics Manufacturing Initiative (iNEMI), testing memory soldered to circuit boards is a major problem for system manufacturers. The ability to thoroughly test, characterize and diagnose problems with soldered-down memory is one of the most pressing problems in the industry.
Testing DDR3 Memory Boundary Scan JTAG eBook
A recent survey asked test engineers to identify their biggest circuit board test problems. Among the top three answers were characterizing and testing soldered-down memories.
Clearly, the ability to thoroughly test, characterize and diagnose faults and failures with soldered-down memory is one of the most pressing problems in the industry. Using DDR3 memory as an example, this eBook discusses how boundary scan test and JTAG methods based on the IEEE 1149.1 standard can be an effective solution.
- Testing memories every step of the way
- What is boundary scan memory test?
- Test and characterize DDR3
More info: Testing DDR3 Memory Boundary Scan JTAG