Researchers have made significant advances in post-epitaxial growth backside clean processing. The research will prepare III-V technology for high-volume manufacturing. The research leading to these accomplishments was conducted at SEMATECH’s facilities at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York.
After a two-year effort to improve process parameters and validating III-V on 200 mm Si VLSI process flows, researchers have identified the key mechanisms to enable a robust backside cleaning process and made significant progress in reducing the likelihood of process cross-contamination that could impact a high-volume manufacturing line.
SEMATECH has developed systematic experiments to identify the key mechanisms of backside contamination, which were then used to engineer robust backside clean process using standard high-volume manufacturing toolsets. At the same time, researchers assessed the environmental, safety and health (ESH) risks of applying and processing compound semiconductor films on silicon dioxide wafers.
Supported by the conventional Si CMOS processing capabilities of CNSE, SEMATECH researchers are now working jointly with chipmakers, equipment and materials suppliers and universities on the ESH and contamination challenges of processing III-V materials in a 300 mm fab in order to enable safe implementation of III-V technology for high-volume manufacturing.
More info: SEMATECH