According to a new white paper, the interplay between the effects of statistical reliability and variability could adversely affect 20nm CMOS SRAM yield. The study also defined a new reliability simulation framework to predict variability and reliability impact that enhances yield. The article was published by Gold Standard Simulations (GSS) and the University of Glasgow Device Modelling Group at the International Physics Reliability Symposium in Monterey, CA.
The title of the technical paper is Interplay Between Statistical Reliability and Variability: A Comprehensive Transistor-to-Circuit Simulation Technology. The research highlights the importance of the interaction between trapped charges and statistical variability in the prediction of transistor and circuit lifetimes. It also describes the development of a unique simulation framework and a set of validated tools that could greatly enhance design and yield predictions in advanced technologies.
According to the study, the interplay amongst individual trapped charges with random discrete dopants (RDD), line edge roughness (LER) and metal gate granularity (MGG) in 20nm CMOS transistors leads to wide dispersions in transistors characteristics and to gigantic random telegraph noise (RTN) amplitudes that adversely affect SRAM yield and reliability. Even a single trapped electron can disturb the information stored in an SRAM memory cell.
Interplay Between Statistical Reliability and Variability Paper
In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability sources. Trapping and detrapping dynamics are reproduced by a kinetic Monte-Carlo engine, which enables oxide degradation simulations such as BTI and RTN phenomenon on large ensembles of atomistic devices. Based on these results compact models are extracted and circuit lifetime projections are derived.
We presented a simulation framework to investigate oxide reliability interplay with statistical variability in nanoscale devices and circuits. BTI degradation traces are reproduced and BTI impact compared with RTN impact on threshold voltage, demonstrating a lack of correlation between both effects. RDF interactions with charged traps lead to a wide dispersion of traps impact on threshold and traps dynamics. The time to device failure is extracted from atomistic simulations, proving again the importance of traps interaction with SV to predict devices lifetime. Atomistic simulations results are used to extract compact models at various stages of oxide degradation, allowing circuit reliability simulations. This synoptic view of the impact of time dependent charge trapping on device-to-circuit performance offers a valuable tool for design and yield projections.
More info: Interplay Between Statistical Reliability and Variability (pdf)