ARM and Cadence Design Systems teamed on the first ARM Cortex-A57 processor for TSMC’s 16-nanometer (nm) FinFET manufacturing process. The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros. Their joint innovations will enable engineers to accelerate product development cycles and take advantage of leading-edge processes and IP.
TSMC’s 16nm FinFET technology enables continued scaling of process technology to feature sizes below 20nm. The test chip was developed with Cadence’s custom, digital and signoff solutions for FinFET process technology. It resulted in several innovations and co-optimizations between manufacturing process, design IP, and design tools.
The Cortex-A57 processor is ARM’s highest-performing processor to date, and is based on the new ARMv8 architecture. It is designed for computing, networking and mobile applications that require high performance at a low-power budget.
The 16nm process using FinFET technology presented new challenges that required significant new development in the design tools. New design rules, RC extraction for 3D transistors, increased complexity of resistance models for interconnect and vias, quantized cell libraries, library characterization that supports new transistor models and double patterning across more layers are some of the challenges that have been addressed in Cadence’s custom, digital and signoff products.