Analog FastSPICE AMS Combines Circuit and Verilog HDL Simulator
Berkeley Design Automation released their Analog FastSPICE AMS. AFS AMS combines the foundry certified Analog FastSPICE circuit simulator with any leading Verilog hardware description language (HDL) simulator to provide full Verilog-AMS language support. It offers simple, fast, and accurate verification of complex nanometer-scale mixed-signal circuits.
Analog AFS AMS features fast mixed-signal verification and nanometer SPICE accuracy. The tool is easy to set-up and run. Design teams using AFS AMS are productive in hours rather than weeks. The tool’s configuration support enables arbitrarily nesting of Verilog-AMS, Verilog-D, Verilog-A, and SPICE netlist formats (all can be run without translation).
Analog FastSPICE AMS is ideal for design teams that have been using limited co-simulation flows, difficult AMS flows, or avoiding mixed-signal simulation altogether because of its complexity. Analog designers are able to continue working within their normal environment.
Analog FastSPICE AMS Features
- Easy mixed-signal setup from command line or leading environment
- Supports all leading Verilog simulators
- Maintain existing digital or analog design-flow
- 5x-10x faster single core, 2x-4x faster multi-core
- >10M-element capacity for SPICE netlist Fastest
- Runs source Verilog-D and SPICE netlist as-is
- Simple, powerful configuration support
- Automated insertion of connect modules
- Arbitrary nesting of analog and digital
- Leverages AFS Platform accuracy performance and capacity advantages
More info: Analog FastSPICE AMS Mixed-Signal Simulator
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